Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS tec...
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Wiley
2021-05-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12012 |
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| author | Marshal Raj Lakshminarayanan Gopalakrishnan Seok‐Bum Ko |
| author_facet | Marshal Raj Lakshminarayanan Gopalakrishnan Seok‐Bum Ko |
| author_sort | Marshal Raj |
| collection | DOAJ |
| description | Abstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs. |
| format | Article |
| id | doaj-art-f17774aa580741908792b0f4de0231a8 |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-05-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-f17774aa580741908792b0f4de0231a82025-02-03T01:29:41ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-05-0115320221310.1049/cdt2.12012Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technologyMarshal Raj0Lakshminarayanan Gopalakrishnan1Seok‐Bum Ko2Department of Electronics and Communication Engineering NIT Tiruchirappalli IndiaDepartment of Electronics and Communication Engineering NIT Tiruchirappalli IndiaDepartment of Electrical and Computer Engineering University of Saskatchewan Saskatoon CanadaAbstract The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law. Quantum‐dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond‐CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND‐NOR logic. In QCA, the NAND‐NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost‐efficient NAND‐NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND‐NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs.https://doi.org/10.1049/cdt2.12012cellular automatahardware description languageslogic gatesnanoelectronicsSRAM chips |
| spellingShingle | Marshal Raj Lakshminarayanan Gopalakrishnan Seok‐Bum Ko Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology IET Computers & Digital Techniques cellular automata hardware description languages logic gates nanoelectronics SRAM chips |
| title | Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology |
| title_full | Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology |
| title_fullStr | Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology |
| title_full_unstemmed | Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology |
| title_short | Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology |
| title_sort | reliable sram using nand nor gate in beyond cmos qca technology |
| topic | cellular automata hardware description languages logic gates nanoelectronics SRAM chips |
| url | https://doi.org/10.1049/cdt2.12012 |
| work_keys_str_mv | AT marshalraj reliablesramusingnandnorgateinbeyondcmosqcatechnology AT lakshminarayanangopalakrishnan reliablesramusingnandnorgateinbeyondcmosqcatechnology AT seokbumko reliablesramusingnandnorgateinbeyondcmosqcatechnology |