APA (7th ed.) Citation

Raheja, S., Dhadich, R., & Rajpal, S. Designing of 2-Stage CPU Scheduler Using Vague Logic. Wiley.

Chicago Style (17th ed.) Citation

Raheja, Supriya, Reena Dhadich, and Smita Rajpal. Designing of 2-Stage CPU Scheduler Using Vague Logic. Wiley.

MLA (9th ed.) Citation

Raheja, Supriya, et al. Designing of 2-Stage CPU Scheduler Using Vague Logic. Wiley.