A High-Speed and Low-Offset Dynamic Latch Comparator
Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In thi...
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| Format: | Article |
| Language: | English |
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Wiley
2014-01-01
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| Series: | The Scientific World Journal |
| Online Access: | http://dx.doi.org/10.1155/2014/258068 |
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| author | Labonnah Farzana Rahman Mamun Bin Ibne Reaz Chia Chieu Yin Mohammad Marufuzzaman Mohammad Anisur Rahman |
| author_facet | Labonnah Farzana Rahman Mamun Bin Ibne Reaz Chia Chieu Yin Mohammad Marufuzzaman Mohammad Anisur Rahman |
| author_sort | Labonnah Farzana Rahman |
| collection | DOAJ |
| description | Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 μm×59.70 μm. |
| format | Article |
| id | doaj-art-e85d480de5754f9ca097974b76538e1c |
| institution | Kabale University |
| issn | 2356-6140 1537-744X |
| language | English |
| publishDate | 2014-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | The Scientific World Journal |
| spelling | doaj-art-e85d480de5754f9ca097974b76538e1c2025-02-03T01:33:05ZengWileyThe Scientific World Journal2356-61401537-744X2014-01-01201410.1155/2014/258068258068A High-Speed and Low-Offset Dynamic Latch ComparatorLabonnah Farzana Rahman0Mamun Bin Ibne Reaz1Chia Chieu Yin2Mohammad Marufuzzaman3Mohammad Anisur Rahman4Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, MalaysiaDepartment of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, MalaysiaMimos Berhad, 57000 Kuala Lumpur, MalaysiaDepartment of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, MalaysiaDepartment of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, MalaysiaCircuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 μm×59.70 μm.http://dx.doi.org/10.1155/2014/258068 |
| spellingShingle | Labonnah Farzana Rahman Mamun Bin Ibne Reaz Chia Chieu Yin Mohammad Marufuzzaman Mohammad Anisur Rahman A High-Speed and Low-Offset Dynamic Latch Comparator The Scientific World Journal |
| title | A High-Speed and Low-Offset Dynamic Latch Comparator |
| title_full | A High-Speed and Low-Offset Dynamic Latch Comparator |
| title_fullStr | A High-Speed and Low-Offset Dynamic Latch Comparator |
| title_full_unstemmed | A High-Speed and Low-Offset Dynamic Latch Comparator |
| title_short | A High-Speed and Low-Offset Dynamic Latch Comparator |
| title_sort | high speed and low offset dynamic latch comparator |
| url | http://dx.doi.org/10.1155/2014/258068 |
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