Comprehensive Analysis on Complementary FET
Complementary Field Effect Transistors (CFETs) have surfaced as a hopeful path to the continued logic area scaling in CMOS technology. This comprehensive review paper explores recent advancements and integration strategies in CFET technology, spanning monolithic CFET processes, vertically stacked na...
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| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10993360/ |
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| Summary: | Complementary Field Effect Transistors (CFETs) have surfaced as a hopeful path to the continued logic area scaling in CMOS technology. This comprehensive review paper explores recent advancements and integration strategies in CFET technology, spanning monolithic CFET processes, vertically stacked nanosheets, and dynamic complementary pin allocation (DCPA) schemes for physical synthesis. Additionally, the paper investigates fabrication and characterization methodologies for vertically stacked junctionless poly-Si nanosheet CMOS inverters for enhanced performance and scalability. This paper delves into the analytical modeling and performance enhancement of CFETs for advanced technology nodes, comparing them with other transistor architectures like lateral GAAFETs. Various CFET configurations, including Hybrid Channel CFETs and sheet-based CFETs, are explored in terms of parasitic capacitance, self-heating effects, and power-performance-area-cost (PPAC) trade-offs. Moreover, the paper discusses recent research advancements in CFET technologies, covering applications, challenges, and prospects. Topics include gate stack solutions for BTI reliability, design rule considerations, heterogeneous stacked RRAM integration, device and system co-optimization, and electrothermal characterization. The semiconductor industry’s transition focuses on the utilization of (EUV) Extreme Ultraviolet lithography for three-nanometer logic processes of CFET and proposing novel CDU and process window analysis techniques. Furthermore, the paper presents a novel CFET-based NAND gate design, termed the double-cell-height (DCH) architecture, to mitigate challenges associated with increased parasitic capacitance and routing congestion. Advancements in process technologies towards (SRAM) Static Random Access Memory cells based on CFET, also design optimization for sub-2nm CMOS nodes are discussed. Additionally, a modeling framework using Artificial Neural Networks (ANN) to estimate process variation effects on stacked CFET devices is proposed, offering insights into CFET research challenges and opportunities. Lastly, thermal and reliability challenges associated with CFETs are explored, along with investigations into CFET design, thermal modeling, electromigration reliability, and process optimization. Emerging technologies such as monolithic 3D integration and machine learning predictions for design optimization are also discussed. Overall, this review paper provides a comprehensive analysis of recent advancements in CFET technology, offering insights into ongoing research efforts and future directions in the field. |
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| ISSN: | 2169-3536 |