V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rul...

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Bibliographic Details
Main Authors: Chao Wang, Yicong Shao, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao, Wei Mao, Yongfu Li
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Open Journal of Circuits and Systems
Subjects:
Verilog-A
Verilog
SystemVerilog
mixed-signal simulation
abstract syntax tree
translator
Online Access:https://ieeexplore.ieee.org/document/10801235/
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https://ieeexplore.ieee.org/document/10801235/

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