V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation
This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rul...
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| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
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| Online Access: | https://ieeexplore.ieee.org/document/10801235/ |
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| author | Chao Wang Yicong Shao Jiajie Huang Wangzilu Lu Zhiwen Gu Longfan Li Yuhang Zhang Jian Zhao Wei Mao Yongfu Li |
| author_facet | Chao Wang Yicong Shao Jiajie Huang Wangzilu Lu Zhiwen Gu Longfan Li Yuhang Zhang Jian Zhao Wei Mao Yongfu Li |
| author_sort | Chao Wang |
| collection | DOAJ |
| description | This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from SystemVerilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over <inline-formula> <tex-math notation="LaTeX">$2{\times }$ </tex-math></inline-formula>. These strengths underscore its significant impact and applicability in the domain of circuit design. |
| format | Article |
| id | doaj-art-e14a5a49011d436f864ed4023f14671e |
| institution | Kabale University |
| issn | 2644-1225 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj-art-e14a5a49011d436f864ed4023f14671e2025-01-21T00:02:49ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252024-01-01538739710.1109/OJCAS.2024.345153010801235V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal SimulationChao Wang0https://orcid.org/0000-0003-0526-0250Yicong Shao1Jiajie Huang2https://orcid.org/0000-0003-4343-0425Wangzilu Lu3https://orcid.org/0000-0003-0046-9004Zhiwen Gu4https://orcid.org/0000-0002-1734-389XLongfan Li5https://orcid.org/0000-0001-9557-7096Yuhang Zhang6https://orcid.org/0000-0002-4101-6207Jian Zhao7https://orcid.org/0000-0003-2140-1236Wei Mao8Yongfu Li9https://orcid.org/0000-0002-6322-8614Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, ChinaDepartment of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, ChinaDepartment of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, ChinaDepartment of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, ChinaDepartment of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, ChinaDepartment of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, ChinaDepartment of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, ChinaDepartment of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, ChinaHangzhou Institute of Technology, Xidian University, Hangzhou, ChinaDepartment of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, ChinaThis paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from SystemVerilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over <inline-formula> <tex-math notation="LaTeX">$2{\times }$ </tex-math></inline-formula>. These strengths underscore its significant impact and applicability in the domain of circuit design.https://ieeexplore.ieee.org/document/10801235/Verilog-AVerilogSystemVerilogmixed-signal simulationabstract syntax treetranslator |
| spellingShingle | Chao Wang Yicong Shao Jiajie Huang Wangzilu Lu Zhiwen Gu Longfan Li Yuhang Zhang Jian Zhao Wei Mao Yongfu Li V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation IEEE Open Journal of Circuits and Systems Verilog-A Verilog SystemVerilog mixed-signal simulation abstract syntax tree translator |
| title | V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation |
| title_full | V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation |
| title_fullStr | V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation |
| title_full_unstemmed | V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation |
| title_short | V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation |
| title_sort | v2va an efficient systemverilog x0026 verilog to verilog a translator for accelerated mixed signal simulation |
| topic | Verilog-A Verilog SystemVerilog mixed-signal simulation abstract syntax tree translator |
| url | https://ieeexplore.ieee.org/document/10801235/ |
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