Reduced switch count multilevel inverter topology for power grid integration - S. Amamra; K. Meghriche; A. Cherifi (Results in Engineering)
This paper presents a novel and efficient topology for multilevel inverters (MLIs), specifically for power system applications, with an emphasis on minimizing the power switches count. The proposed topology integrates a cascaded configuration of three-phase traditional H-bridge inverters with a multistring multilevel inverter. This innovative design significantly reduces harmonic distortion, energy losses, system dimensions, and both the cost and complexity of the hardware, key considerations for practical grid integration. Simulations conducted in MATLAB/Simulink verify the proposed topology’s capability to achieve up to six, twelve and eighteen voltage levels with the connection of only three, five and seven DC sources. This feature offers substantial improvements in power quality and overall system efficiency. Experimental validation of the developed prototype further confirms a notable reduction in harmonic distortion, achieving an approximate 15 % and 1.2 % voltage and current THD respectively. These findings highlight the effectiveness of the proposed topology in enhancing grid integration performance by minimizing undesirable harmonics and improving system reliability and sustainability. Additionally, the simplified hardware and cost-efficiency position this approach as a promising solution for large-scale different DC sources integration into power grid.