AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow
The increasing complexity of algorithms in embedded applications has amplified the demand for high-performance computing. Heterogeneous embedded systems, particularly FPGA-based systems-on-chip (SoCs), enhance execution speed by integrating hardware accelerator intellectual property (IP) cores. Howe...
Saved in:
| Main Authors: | David Berrazueta-Mena, Byron Navas |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2025-05-01
|
| Series: | Computers |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2073-431X/14/5/189 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
High-Throughput ORB Feature Extraction on Zynq SoC for Real-Time Structure-from-Motion Pipelines
by: Panteleimon Stamatakis, et al.
Published: (2025-05-01) -
Image Processing Hardware Acceleration—A Review of Operations Involved and Current Hardware Approaches
by: Costin-Emanuel Vasile, et al.
Published: (2024-11-01) -
FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs
by: Mustafa Tasci, et al.
Published: (2025-01-01) -
Hardware-accelerated real-time IP flow measurement method for multi-core architecture
by: ZHU Chao1, et al.
Published: (2008-01-01) -
FPGA Acceleration With Hessian-Based Comprehensive Intra-Layer Mixed-Precision Quantization for Transformer Models
by: Woohong Byun, et al.
Published: (2025-01-01)