Dual Scalable Annealing Processing System That Scales Number of Spins and Interaction Bit Width Simultaneously - Dong Cui; Taichi Megumi; Akari Endo; Takayuki Kawahara (IEEE Access)
Annealing processors (APs) specialized for solving combinatorial optimization problems (COPs) have been gaining attention. Among them, APs that use a fully-coupled Ising model are in demand because of their versatility. However, due to the complexity of the spin couplings, challenges remain in achieving systems that balance both capacity (number of spins) and precision (interaction bit width). Previous studies have implemented annealing systems that only increase the number of spins using a scalable structure by distributing the calculation across multiple chips. This study proposes a dual scalable annealing processing system (DSAPS) that can simultaneously scale both capacity and precision using the same scalable structure. This demonstrates a new direction that combines both the number of spins and interaction bit width. A board implementation utilized spin threads to create two types of DSAPS: DSAPS #1, with 2048 spins, 10-bit interactions and four threads, and DSAPS #2, with 1024 spins, 37-bit interactions and two threads. Scaled MAX-CUT problems were used for operational validation, achieving an accuracy of over 99% compared with theoretical values. In another validation using the 0-1 knapsack problem, DSAPS #1 achieved an average deviation of over 99% relative to the knapsack capacity, whereas DSAPS #2 reduced the average deviation to 0.73%. This result is close to the average deviation of 0.40% obtained with an annealing emulation on a CPU (64-bit), demonstrating the significance of implementing DSAPSs suited to the characteristics of COPs.