Analysis and Verilog-A Modeling of Floating-Gate Transistors
Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circu...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10818976/ |
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| Summary: | Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circuits typically involves extensive SPICE-based simulations, yet integrating and calibrating floating-gate transistors post-fabrication is a common practice. To bridge this gap, we present a Verilog-A model based on empirical measurements for a floating-gate transistor fabricated using a 65 nm CMOS process. This model incorporates mechanisms for hot-electron injection and Fowler-Nordheim tunneling, and accurately predicts retention time, thus facilitating the design of adaptive peripheral circuits. Our findings offer insights into optimizing floating-gate transistors for enhanced programming efficiency and reduced area consumption. |
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| ISSN: | 2644-1225 |