A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design
This paper proposes a physical charge-based analytical MOSFET threshold voltage model that explicitly incorporates interface-trapped charges which have been identified as playing a dominant role in defining threshold voltage trends in deep cryogenic temperatures. The model retains standard threshold...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10416243/ |
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| author | Hao Su Yiyuan Cai Shenghua Zhou Guangchong Hu Yu He Yunfeng Xie Yuhuan Lin Chunhui Li Tianqi Zhao Jun Lan Wenhui Wang Wenxin Li Feichi Zhou Xiaoguang Liu Longyang Lin Yida Li Hongyu Yu Kai Chen |
| author_facet | Hao Su Yiyuan Cai Shenghua Zhou Guangchong Hu Yu He Yunfeng Xie Yuhuan Lin Chunhui Li Tianqi Zhao Jun Lan Wenhui Wang Wenxin Li Feichi Zhou Xiaoguang Liu Longyang Lin Yida Li Hongyu Yu Kai Chen |
| author_sort | Hao Su |
| collection | DOAJ |
| description | This paper proposes a physical charge-based analytical MOSFET threshold voltage model that explicitly incorporates interface-trapped charges which have been identified as playing a dominant role in defining threshold voltage trends in deep cryogenic temperatures. The model retains standard threshold voltage definition by various charges across the MOSFET capacitor while being analytical in its form, therefore, suitable for cryogenic CMOS VLSI design. Consequently, a model covering each and all above characteristics is proposed for the first time. Excellent fit between the model and measurement data from 180-nm bulk foundry devices is shown from room temperature to 4 K. |
| format | Article |
| id | doaj-art-daed3e0a200349689d0a22fad68b624a |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-daed3e0a200349689d0a22fad68b624a2025-01-29T00:00:36ZengIEEEIEEE Journal of the Electron Devices Society2168-67342024-01-011285986710.1109/JEDS.2024.335966410416243A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS DesignHao Su0https://orcid.org/0000-0002-2444-7128Yiyuan Cai1Shenghua Zhou2Guangchong Hu3Yu He4Yunfeng Xie5https://orcid.org/0000-0003-1189-4321Yuhuan Lin6https://orcid.org/0000-0002-5117-5893Chunhui Li7Tianqi Zhao8Jun Lan9https://orcid.org/0000-0003-4824-8243Wenhui Wang10https://orcid.org/0000-0002-0571-0912Wenxin Li11Feichi Zhou12Xiaoguang Liu13https://orcid.org/0000-0002-0935-3094Longyang Lin14https://orcid.org/0000-0002-4702-737XYida Li15https://orcid.org/0000-0002-5675-582XHongyu Yu16Kai Chen17School of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaShenzhen Institute for Quantum Science and Engineering, Southern University of Science and Technology, Shenzhen, ChinaIntegrated Circuits and Electronics Center, International Quantum Academy, Shenzhen, ChinaShenzhen Institute for Quantum Science and Engineering, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaShenzhen Institute for Quantum Science and Engineering, Southern University of Science and Technology, Shenzhen, ChinaShenzhen Institute for Quantum Science and Engineering, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaThis paper proposes a physical charge-based analytical MOSFET threshold voltage model that explicitly incorporates interface-trapped charges which have been identified as playing a dominant role in defining threshold voltage trends in deep cryogenic temperatures. The model retains standard threshold voltage definition by various charges across the MOSFET capacitor while being analytical in its form, therefore, suitable for cryogenic CMOS VLSI design. Consequently, a model covering each and all above characteristics is proposed for the first time. Excellent fit between the model and measurement data from 180-nm bulk foundry devices is shown from room temperature to 4 K.https://ieeexplore.ieee.org/document/10416243/Bulk CMOSthreshold voltagecryogenicanalyticalcompactuniversal |
| spellingShingle | Hao Su Yiyuan Cai Shenghua Zhou Guangchong Hu Yu He Yunfeng Xie Yuhuan Lin Chunhui Li Tianqi Zhao Jun Lan Wenhui Wang Wenxin Li Feichi Zhou Xiaoguang Liu Longyang Lin Yida Li Hongyu Yu Kai Chen A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design IEEE Journal of the Electron Devices Society Bulk CMOS threshold voltage cryogenic analytical compact universal |
| title | A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design |
| title_full | A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design |
| title_fullStr | A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design |
| title_full_unstemmed | A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design |
| title_short | A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design |
| title_sort | physical charge based analytical threshold voltage model for cryogenic cmos design |
| topic | Bulk CMOS threshold voltage cryogenic analytical compact universal |
| url | https://ieeexplore.ieee.org/document/10416243/ |
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