A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design

A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design

This paper proposes a physical charge-based analytical MOSFET threshold voltage model that explicitly incorporates interface-trapped charges which have been identified as playing a dominant role in defining threshold voltage trends in deep cryogenic temperatures. The model retains standard threshold...

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Bibliographic Details
Main Authors: Hao Su, Yiyuan Cai, Shenghua Zhou, Guangchong Hu, Yu He, Yunfeng Xie, Yuhuan Lin, Chunhui Li, Tianqi Zhao, Jun Lan, Wenhui Wang, Wenxin Li, Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, Kai Chen
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Bulk CMOS
threshold voltage
cryogenic
analytical
compact
universal
Online Access:https://ieeexplore.ieee.org/document/10416243/
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Summary:This paper proposes a physical charge-based analytical MOSFET threshold voltage model that explicitly incorporates interface-trapped charges which have been identified as playing a dominant role in defining threshold voltage trends in deep cryogenic temperatures. The model retains standard threshold voltage definition by various charges across the MOSFET capacitor while being analytical in its form, therefore, suitable for cryogenic CMOS VLSI design. Consequently, a model covering each and all above characteristics is proposed for the first time. Excellent fit between the model and measurement data from 180-nm bulk foundry devices is shown from room temperature to 4 K.
ISSN:2168-6734

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