Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques
In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force la...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2014-01-01
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| Series: | The Scientific World Journal |
| Online Access: | http://dx.doi.org/10.1155/2014/164059 |
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| _version_ | 1832556163412000768 |
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| author | Julio Dondo Gazzano Fernando Rincon Carlos Vaderrama Felix Villanueva Julian Caba Juan Carlos Lopez |
| author_facet | Julio Dondo Gazzano Fernando Rincon Carlos Vaderrama Felix Villanueva Julian Caba Juan Carlos Lopez |
| author_sort | Julio Dondo Gazzano |
| collection | DOAJ |
| description | In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration. |
| format | Article |
| id | doaj-art-d69e852b0614458cb3ccd80a4e7a698d |
| institution | Kabale University |
| issn | 2356-6140 1537-744X |
| language | English |
| publishDate | 2014-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | The Scientific World Journal |
| spelling | doaj-art-d69e852b0614458cb3ccd80a4e7a698d2025-02-03T05:46:17ZengWileyThe Scientific World Journal2356-61401537-744X2014-01-01201410.1155/2014/164059164059Facilitating Preemptive Hardware System Design Using Partial Reconfiguration TechniquesJulio Dondo Gazzano0Fernando Rincon1Carlos Vaderrama2Felix Villanueva3Julian Caba4Juan Carlos Lopez5University of Castilla-La Mancha, 13071 Ciudad Real, SpainUniversity of Castilla-La Mancha, 13071 Ciudad Real, SpainElectronics Department, Polytechnic Faculty, University of Mons, Mons, BelgiumUniversity of Castilla-La Mancha, 13071 Ciudad Real, SpainUniversity of Castilla-La Mancha, 13071 Ciudad Real, SpainUniversity of Castilla-La Mancha, 13071 Ciudad Real, SpainIn FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration.http://dx.doi.org/10.1155/2014/164059 |
| spellingShingle | Julio Dondo Gazzano Fernando Rincon Carlos Vaderrama Felix Villanueva Julian Caba Juan Carlos Lopez Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques The Scientific World Journal |
| title | Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques |
| title_full | Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques |
| title_fullStr | Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques |
| title_full_unstemmed | Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques |
| title_short | Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques |
| title_sort | facilitating preemptive hardware system design using partial reconfiguration techniques |
| url | http://dx.doi.org/10.1155/2014/164059 |
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