Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications
Using extensive Monte-Carlo simulations with a nucleation-limited-switching (NLS) ferroelectric model and considering cycle-to-cycle variations, this paper constructs and analyzes the intrinsic conductance (G<sub>DS</sub>) response of stacked-nanosheet FeFET synapses with emphasis on the...
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of Nanotechnology |
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| Online Access: | https://ieeexplore.ieee.org/document/10528861/ |
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| author | Heng Li Lin Pin Su |
| author_facet | Heng Li Lin Pin Su |
| author_sort | Heng Li Lin |
| collection | DOAJ |
| description | Using extensive Monte-Carlo simulations with a nucleation-limited-switching (NLS) ferroelectric model and considering cycle-to-cycle variations, this paper constructs and analyzes the intrinsic conductance (G<sub>DS</sub>) response of stacked-nanosheet FeFET synapses with emphasis on the challenging identical-pulse stimulation. Our study indicates that the interlayer oxide thickness of the FeFET and the saturation polarization of the ferroelectric are crucial to the linearity and symmetry of the intrinsic G<sub>DS</sub> response. With the stacked-nanosheet architecture, the maximum-to-minimum conductance ratio in the G<sub>DS</sub> response can be boosted by increasing the number of channel tiers without footprint penalty. For a stacked-nanosheet FeFET synapse with an area ratio effect, the G<sub>DS</sub> response can be further engineered by varying the tier number. In addition, the immunity to cycle-to-cycle variations and the noise margin for each state in the G<sub>DS</sub> response can also be improved by increasing the number of tiers. Our study may provide insights for future FeFET synapse design for analog computing. |
| format | Article |
| id | doaj-art-cfba77672a8246b4bb1aa257e1343331 |
| institution | Kabale University |
| issn | 2644-1292 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Nanotechnology |
| spelling | doaj-art-cfba77672a8246b4bb1aa257e13433312025-01-24T00:02:22ZengIEEEIEEE Open Journal of Nanotechnology2644-12922024-01-015172210.1109/OJNANO.2024.339955910528861Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic ApplicationsHeng Li Lin0https://orcid.org/0009-0008-4277-5687Pin Su1https://orcid.org/0000-0002-8213-4103Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, TaiwanInstitute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, TaiwanUsing extensive Monte-Carlo simulations with a nucleation-limited-switching (NLS) ferroelectric model and considering cycle-to-cycle variations, this paper constructs and analyzes the intrinsic conductance (G<sub>DS</sub>) response of stacked-nanosheet FeFET synapses with emphasis on the challenging identical-pulse stimulation. Our study indicates that the interlayer oxide thickness of the FeFET and the saturation polarization of the ferroelectric are crucial to the linearity and symmetry of the intrinsic G<sub>DS</sub> response. With the stacked-nanosheet architecture, the maximum-to-minimum conductance ratio in the G<sub>DS</sub> response can be boosted by increasing the number of channel tiers without footprint penalty. For a stacked-nanosheet FeFET synapse with an area ratio effect, the G<sub>DS</sub> response can be further engineered by varying the tier number. In addition, the immunity to cycle-to-cycle variations and the noise margin for each state in the G<sub>DS</sub> response can also be improved by increasing the number of tiers. Our study may provide insights for future FeFET synapse design for analog computing.https://ieeexplore.ieee.org/document/10528861/Stacked nanosheetferroelectric field-effect transistor (FeFET)analog synapseneuromorphic computing |
| spellingShingle | Heng Li Lin Pin Su Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications IEEE Open Journal of Nanotechnology Stacked nanosheet ferroelectric field-effect transistor (FeFET) analog synapse neuromorphic computing |
| title | Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications |
| title_full | Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications |
| title_fullStr | Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications |
| title_full_unstemmed | Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications |
| title_short | Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications |
| title_sort | analysis and design of fefet synapse with stacked nanosheet architecture considering cycle to cycle variations for neuromorphic applications |
| topic | Stacked nanosheet ferroelectric field-effect transistor (FeFET) analog synapse neuromorphic computing |
| url | https://ieeexplore.ieee.org/document/10528861/ |
| work_keys_str_mv | AT henglilin analysisanddesignoffefetsynapsewithstackednanosheetarchitectureconsideringcycletocyclevariationsforneuromorphicapplications AT pinsu analysisanddesignoffefetsynapsewithstackednanosheetarchitectureconsideringcycletocyclevariationsforneuromorphicapplications |