Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications
Using extensive Monte-Carlo simulations with a nucleation-limited-switching (NLS) ferroelectric model and considering cycle-to-cycle variations, this paper constructs and analyzes the intrinsic conductance (G<sub>DS</sub>) response of stacked-nanosheet FeFET synapses with emphasis on the...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
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| Series: | IEEE Open Journal of Nanotechnology |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10528861/ |
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| Summary: | Using extensive Monte-Carlo simulations with a nucleation-limited-switching (NLS) ferroelectric model and considering cycle-to-cycle variations, this paper constructs and analyzes the intrinsic conductance (G<sub>DS</sub>) response of stacked-nanosheet FeFET synapses with emphasis on the challenging identical-pulse stimulation. Our study indicates that the interlayer oxide thickness of the FeFET and the saturation polarization of the ferroelectric are crucial to the linearity and symmetry of the intrinsic G<sub>DS</sub> response. With the stacked-nanosheet architecture, the maximum-to-minimum conductance ratio in the G<sub>DS</sub> response can be boosted by increasing the number of channel tiers without footprint penalty. For a stacked-nanosheet FeFET synapse with an area ratio effect, the G<sub>DS</sub> response can be further engineered by varying the tier number. In addition, the immunity to cycle-to-cycle variations and the noise margin for each state in the G<sub>DS</sub> response can also be improved by increasing the number of tiers. Our study may provide insights for future FeFET synapse design for analog computing. |
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| ISSN: | 2644-1292 |