A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology
This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet targ...
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10772610/ |
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| author | Yongxin Li Tianyu Wang Mostafa Gamal Ahmed Ruhao Xia Kyu-Sang Park Mahmoud A. Khalil Sashank Krishnamurthy Zhe Xuan Ganesh Balamurugan Pavan Kumar Hanumolu |
| author_facet | Yongxin Li Tianyu Wang Mostafa Gamal Ahmed Ruhao Xia Kyu-Sang Park Mahmoud A. Khalil Sashank Krishnamurthy Zhe Xuan Ganesh Balamurugan Pavan Kumar Hanumolu |
| author_sort | Yongxin Li |
| collection | DOAJ |
| description | This article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> A rms, an averaged INRC density of 6.4 pA/<inline-formula> <tex-math notation="LaTeX">$\sqrt {\text {Hz}}$ </tex-math></inline-formula>, consumes 11.4 mW of power, and provides 87-dB<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s. |
| format | Article |
| id | doaj-art-ca8a496a29b441cf9d1bf82ca63a9d24 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-ca8a496a29b441cf9d1bf82ca63a9d242025-01-25T00:03:07ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01432833910.1109/OJSSCS.2024.351047810772610A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design MethodologyYongxin Li0https://orcid.org/0000-0003-3812-9793Tianyu Wang1Mostafa Gamal Ahmed2https://orcid.org/0000-0002-2636-4713Ruhao Xia3https://orcid.org/0000-0003-3694-0160Kyu-Sang Park4https://orcid.org/0000-0003-2515-4682Mahmoud A. Khalil5Sashank Krishnamurthy6Zhe Xuan7https://orcid.org/0000-0003-4583-4060Ganesh Balamurugan8Pavan Kumar Hanumolu9https://orcid.org/0000-0001-7424-1075Department of ECE, University of Illinois at Urbana-Champaign, Urbana, IL, USADepartment of ECE, University of Illinois at Urbana-Champaign, Urbana, IL, USADepartment of ECE, University of Illinois at Urbana-Champaign, Urbana, IL, USADepartment of ECE, University of Illinois at Urbana-Champaign, Urbana, IL, USADepartment of ECE, University of Illinois at Urbana-Champaign, Urbana, IL, USADepartment of ECE, University of Illinois at Urbana-Champaign, Urbana, IL, USAIntel Corporation, Hillsboro, OR, USAIntel Corporation, Hillsboro, OR, USAIntel Corporation, Hillsboro, OR, USADepartment of ECE, University of Illinois at Urbana-Champaign, Urbana, IL, USAThis article presents a systematic design methodology for transimpedance amplifiers (TIAs) based on two-port parameters, enabling efficient exploration of complex TIA architectures, including multistage forward amplifiers, and facilitating the identification of optimal design parameters to meet target specifications. Using this methodology, an analog front-end (AFE) with a low-noise, low-power, high-gain TIA was designed in a 22-nm FinFET process. Post-layout simulations show that the AFE achieves an input-referred noise current (INRC) of 0.78-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> A rms, an averaged INRC density of 6.4 pA/<inline-formula> <tex-math notation="LaTeX">$\sqrt {\text {Hz}}$ </tex-math></inline-formula>, consumes 11.4 mW of power, and provides 87-dB<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> transimpedance gain with a 14.2-GHz bandwidth. The simulated TIA performance closely matches the results predicted by the design methodology, validating its accuracy and effectiveness. A prototype optical receiver featuring this AFE was fabricated in a 22-nm process and measured to achieve an OMA sensitivity of −11.6 dBm with an energy efficiency of 0.55 pJ/bit at a data rate of 40 Gb/s.https://ieeexplore.ieee.org/document/10772610/CMOSdesign methodologyduobinaryoptical receivertransimpedance amplifier (TIA)two-port networks |
| spellingShingle | Yongxin Li Tianyu Wang Mostafa Gamal Ahmed Ruhao Xia Kyu-Sang Park Mahmoud A. Khalil Sashank Krishnamurthy Zhe Xuan Ganesh Balamurugan Pavan Kumar Hanumolu A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology IEEE Open Journal of the Solid-State Circuits Society CMOS design methodology duobinary optical receiver transimpedance amplifier (TIA) two-port networks |
| title | A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology |
| title_full | A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology |
| title_fullStr | A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology |
| title_full_unstemmed | A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology |
| title_short | A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology |
| title_sort | x2212 11 6 dbm oma sensitivity 0 55 pj bit 40 gb s optical receiver designed using a 2 port parameter based design methodology |
| topic | CMOS design methodology duobinary optical receiver transimpedance amplifier (TIA) two-port networks |
| url | https://ieeexplore.ieee.org/document/10772610/ |
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