An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking
This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, the n...
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2021-01-01
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author | Muhammad Riaz Ur Rehman Arash Hejazi Imran Ali Muhammad Asif Seongjin Oh Pervesh Kumar Younggun Pu Sang-Sun Yoo Keum Cheol Hwang Youngoo Yang Yeonjae Jung Hyungki Huh Seokkee Kim Joon-Mo Yoo Kang-Yoon Lee |
author_facet | Muhammad Riaz Ur Rehman Arash Hejazi Imran Ali Muhammad Asif Seongjin Oh Pervesh Kumar Younggun Pu Sang-Sun Yoo Keum Cheol Hwang Youngoo Yang Yeonjae Jung Hyungki Huh Seokkee Kim Joon-Mo Yoo Kang-Yoon Lee |
author_sort | Muhammad Riaz Ur Rehman |
collection | DOAJ |
description | This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, the need for Time-to-Digital Converter (TDC) is eliminated through providing the CFTL circuitry. This feature makes the design compact, low power, and suitable for IoT applications. The proposed design is based on a synthesizable pulse injection and frequency-locked loop along with an ultra-low-power LC Digitally-Controlled Oscillator (LC-DCO). The presented CFTL circuit adjusts the frequency of the DCO continuously and prevents the frequency drift after the reference injection. Inside the designed LC-DCO core, the power consumption is minimized by optimizing the <inline-formula> <tex-math notation="LaTeX">$\text{g}_{\mathrm {m}}~/\text{I}_{\mathrm {D}}$ </tex-math></inline-formula> and adjusting the power supply to 0.5 V. The proposed ILFM based ADPLL is fabricated in 55 nm CMOS technology and covers the operational frequency range of 2.402 GHz to 2.480 GHz with a reference frequency of 32 MHz. The measured phase noise performance of the ADPLL is −111.15 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.4 GHz. It consumes only 0.46 mW power with an active area of 0.129 mm<sup>2</sup>. |
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institution | Kabale University |
issn | 2169-3536 |
language | English |
publishDate | 2021-01-01 |
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spelling | doaj-art-c9ac4dc344304972b4c5c288c7a90f582025-01-30T00:01:05ZengIEEEIEEE Access2169-35362021-01-01915298415299210.1109/ACCESS.2021.31231679585455An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency TrackingMuhammad Riaz Ur Rehman0https://orcid.org/0000-0002-2128-0115Arash Hejazi1https://orcid.org/0000-0002-5852-5761Imran Ali2https://orcid.org/0000-0002-4705-9988Muhammad Asif3https://orcid.org/0000-0002-4888-9721Seongjin Oh4https://orcid.org/0000-0001-8879-6661Pervesh Kumar5https://orcid.org/0000-0003-1858-1707Younggun Pu6https://orcid.org/0000-0001-5190-4462Sang-Sun Yoo7https://orcid.org/0000-0001-5178-4392Keum Cheol Hwang8https://orcid.org/0000-0002-8074-1137Youngoo Yang9https://orcid.org/0000-0003-3463-0687Yeonjae Jung10Hyungki Huh11Seokkee Kim12Joon-Mo Yoo13Kang-Yoon Lee14https://orcid.org/0000-0001-9777-6953College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Smart Automobile, Pyeongtaek University, Pyeongtaek, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaThis paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, the need for Time-to-Digital Converter (TDC) is eliminated through providing the CFTL circuitry. This feature makes the design compact, low power, and suitable for IoT applications. The proposed design is based on a synthesizable pulse injection and frequency-locked loop along with an ultra-low-power LC Digitally-Controlled Oscillator (LC-DCO). The presented CFTL circuit adjusts the frequency of the DCO continuously and prevents the frequency drift after the reference injection. Inside the designed LC-DCO core, the power consumption is minimized by optimizing the <inline-formula> <tex-math notation="LaTeX">$\text{g}_{\mathrm {m}}~/\text{I}_{\mathrm {D}}$ </tex-math></inline-formula> and adjusting the power supply to 0.5 V. The proposed ILFM based ADPLL is fabricated in 55 nm CMOS technology and covers the operational frequency range of 2.402 GHz to 2.480 GHz with a reference frequency of 32 MHz. The measured phase noise performance of the ADPLL is −111.15 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.4 GHz. It consumes only 0.46 mW power with an active area of 0.129 mm<sup>2</sup>.https://ieeexplore.ieee.org/document/9585455/ADPLLinjection locked frequency multiplierlow powersmall areaInternet of Thingsdigitally-controlled oscillator |
spellingShingle | Muhammad Riaz Ur Rehman Arash Hejazi Imran Ali Muhammad Asif Seongjin Oh Pervesh Kumar Younggun Pu Sang-Sun Yoo Keum Cheol Hwang Youngoo Yang Yeonjae Jung Hyungki Huh Seokkee Kim Joon-Mo Yoo Kang-Yoon Lee An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking IEEE Access ADPLL injection locked frequency multiplier low power small area Internet of Things digitally-controlled oscillator |
title | An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking |
title_full | An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking |
title_fullStr | An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking |
title_full_unstemmed | An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking |
title_short | An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking |
title_sort | ultra low power 2 4 ghz all digital phase locked loop with injection locked frequency multiplier and continuous frequency tracking |
topic | ADPLL injection locked frequency multiplier low power small area Internet of Things digitally-controlled oscillator |
url | https://ieeexplore.ieee.org/document/9585455/ |
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