FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review

In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic...

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Main Authors: Abdulmajeed Adil Yazdeen, Subhi R. M. Zeebaree, Mohammed Mohammed Sadeeq, Shakir Fattah Kak, Omar M. Ahmed, Rizgar R. Zebari
Format: Article
Language:English
Published: Qubahan 2021-03-01
Series:Qubahan Academic Journal
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Online Access:https://journal.qubahan.com/index.php/qaj/article/view/38
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_version_ 1832544506942062592
author Abdulmajeed Adil Yazdeen
Subhi R. M. Zeebaree
Mohammed Mohammed Sadeeq
Shakir Fattah Kak
Omar M. Ahmed
Rizgar R. Zebari
author_facet Abdulmajeed Adil Yazdeen
Subhi R. M. Zeebaree
Mohammed Mohammed Sadeeq
Shakir Fattah Kak
Omar M. Ahmed
Rizgar R. Zebari
author_sort Abdulmajeed Adil Yazdeen
collection DOAJ
description In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic encryption, symmetrical block chips play an essential role. Data Encryption Standard (DES) and Advanced Encryption Standard (AES) ensure privacy encryption underlying data protection standards. The DES and the AES provide information security. DES and AES have the distinction of being introduced in both hardware and applications. DES and AES hardware implementation has many advantages, such as increased performance and improved safety. This paper provides an exhaustive study of the implementation by DES and AES of field programming gate arrays (FPGAs) using both DES and AES. Since FPGAs can be defined as just one mission, computers are superior to them.
format Article
id doaj-art-c5dd3ef3e8204a1c866d8382a6a97460
institution Kabale University
issn 2709-8206
language English
publishDate 2021-03-01
publisher Qubahan
record_format Article
series Qubahan Academic Journal
spelling doaj-art-c5dd3ef3e8204a1c866d8382a6a974602025-02-03T10:12:56ZengQubahanQubahan Academic Journal2709-82062021-03-011210.48161/qaj.v1n2a3838FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A ReviewAbdulmajeed Adil Yazdeen0Subhi R. M. Zeebaree 1Mohammed Mohammed Sadeeq2Shakir Fattah Kak3Omar M. Ahmed4Rizgar R. Zebari5Dept. Information Technology Management Duhok Polytechnic University Duhok, Iraq IT Dept., Duhok Polytechnic University, Duhok, IraqDuhok Polytechnic UniversityDept. Information Technology, Duhok Polytechnic University, Akre-Duhok, IraqDept. Information Technology, Duhok Polytechnic University, Duhok, IraqResearch and Development Center, Nawroz University, Duhok, Iraq In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic encryption, symmetrical block chips play an essential role. Data Encryption Standard (DES) and Advanced Encryption Standard (AES) ensure privacy encryption underlying data protection standards. The DES and the AES provide information security. DES and AES have the distinction of being introduced in both hardware and applications. DES and AES hardware implementation has many advantages, such as increased performance and improved safety. This paper provides an exhaustive study of the implementation by DES and AES of field programming gate arrays (FPGAs) using both DES and AES. Since FPGAs can be defined as just one mission, computers are superior to them. https://journal.qubahan.com/index.php/qaj/article/view/38Cryptography, DES algorithm, AES algorithm FPGAs Implementations, VHDL.
spellingShingle Abdulmajeed Adil Yazdeen
Subhi R. M. Zeebaree
Mohammed Mohammed Sadeeq
Shakir Fattah Kak
Omar M. Ahmed
Rizgar R. Zebari
FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review
Qubahan Academic Journal
Cryptography, DES algorithm, AES algorithm FPGAs Implementations, VHDL.
title FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review
title_full FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review
title_fullStr FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review
title_full_unstemmed FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review
title_short FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review
title_sort fpga implementations for data encryption and decryption via concurrent and parallel computation a review
topic Cryptography, DES algorithm, AES algorithm FPGAs Implementations, VHDL.
url https://journal.qubahan.com/index.php/qaj/article/view/38
work_keys_str_mv AT abdulmajeedadilyazdeen fpgaimplementationsfordataencryptionanddecryptionviaconcurrentandparallelcomputationareview
AT subhirmzeebaree fpgaimplementationsfordataencryptionanddecryptionviaconcurrentandparallelcomputationareview
AT mohammedmohammedsadeeq fpgaimplementationsfordataencryptionanddecryptionviaconcurrentandparallelcomputationareview
AT shakirfattahkak fpgaimplementationsfordataencryptionanddecryptionviaconcurrentandparallelcomputationareview
AT omarmahmed fpgaimplementationsfordataencryptionanddecryptionviaconcurrentandparallelcomputationareview
AT rizgarrzebari fpgaimplementationsfordataencryptionanddecryptionviaconcurrentandparallelcomputationareview