High-Speed Wireline Links—Part I: Modeling

In a wireline link, we wish to model a wide variety of architectures and optimize their parameters, such as the feedforward equalizer and decision feedback equalizer tap coefficients, continuous-time linear equalizer frequency response, termination impedances, and possibly maximum-likelihood sequenc...

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Bibliographic Details
Main Authors: Hossein Shakiba, Davide Tonietto, Ali Sheikholeslami
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Open Journal of the Solid-State Circuits Society
Subjects:
Online Access:https://ieeexplore.ieee.org/document/10608184/
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Summary:In a wireline link, we wish to model a wide variety of architectures and optimize their parameters, such as the feedforward equalizer and decision feedback equalizer tap coefficients, continuous-time linear equalizer frequency response, termination impedances, and possibly maximum-likelihood sequence estimation parameters, for a given channel and within a given set of constraints as dictated by the application requirements so as to minimize the link’s bit error rate. The modulation can be any of the PAM signaling schemes, such as NRZ or 4-PAM. To this end, we first model a general link architecture in Part I, and then optimize the link parameters in Part II.
ISSN:2644-1349