AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC
With the evolution of technology, the system complexity increased and the application fields of the embedded system expanded. Current applications need a high degree of performance, flexibility, and efficient development environments. Today, reconfigurable logic allows to meet the on-chip processing...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2011-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2011/425401 |
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| Summary: | With the evolution of technology, the system
complexity increased and the application fields of the embedded
system expanded. Current applications need a high
degree of performance, flexibility, and efficient development
environments. Today, reconfigurable logic allows to meet the
on-chip processing requirements with new benefits resulting
from partial and dynamic reconfiguration. But the dimension
introduced in the design of these systems requires more
abstraction to manage their complexity and efficient models
to provide reliable preliminary estimations.
While classical multiprocessor systems can be modeled
without difficulty, the use of partial run-time reconfiguration
in heterogeneous flexible system-on-chips is generally not
covered. The contribution of this paper is to address this with
an extension of the AADL language able to model the reconfigurable
logic, possibly considering dynamic reconfiguration and
power consumption requirements. The proposed AADL model
is divided into three levels to provide a generic and hierarchical
approach separating the static and dynamic parts of current
FPGAs. These levels are exposed in detail and illustrated on a
concrete example of FPGA device. The design space exploration
of an application deployment using this model is also presented. |
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| ISSN: | 1687-7195 1687-7209 |