An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO
In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is presented. For locking DCO frequency closest to the ta...
Saved in:
| Main Authors: | , , , , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9097205/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832582402753429504 |
|---|---|
| author | Imran Ali Hamed Abbasizadeh Muhammad Riaz Ur Rehman Muhammad Asif Seong Jin Oh Young Gun Pu Minjae Lee Keum Cheol Hwang Youngoo Yang Kang-Yoon Lee |
| author_facet | Imran Ali Hamed Abbasizadeh Muhammad Riaz Ur Rehman Muhammad Asif Seong Jin Oh Young Gun Pu Minjae Lee Keum Cheol Hwang Youngoo Yang Kang-Yoon Lee |
| author_sort | Imran Ali |
| collection | DOAJ |
| description | In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is presented. For locking DCO frequency closest to the target channel, it adaptively controls capacitor banks with binary algorithm. With decrease in frequency resolution, DCO clock counts for each capacitor bank bit evaluation dynamically increases with the proposed technique for accurate frequency tracking. For compensating PVT variations and finding the BLE frequency deviation, the configurable digital DCO gain estimation is incorporated. The low power and constant current DCO operates in sub-threshold region and its power consumption is minimized by <inline-formula> <tex-math notation="LaTeX">$g_{m}/I_{D}$ </tex-math></inline-formula> methodology optimization, constant current source for limiting current in DCO core through adaptive low-dropout regulator (LDO) and lowering the supply voltage. The proposed design is integrated in an ADPLL for BLE transceiver and it is fabricated with 1P6M TSMC 55 nm CMOS technology. The all-digital adaptive FLL is fully synthesizable and its area is <inline-formula> <tex-math notation="LaTeX">$1800~\mu \text{m}^{2}$ </tex-math></inline-formula> with 1.233 K gate count. The RMS current consumption is <inline-formula> <tex-math notation="LaTeX">$103.32~\mu \text{A}$ </tex-math></inline-formula> from 1 V voltage supply with <inline-formula> <tex-math notation="LaTeX">$103.32~\mu \text{W}$ </tex-math></inline-formula> power requirement. The experimental results reveal, DCO draws <inline-formula> <tex-math notation="LaTeX">$480~\mu \text{A}$ </tex-math></inline-formula> current from 0.55 V supply voltage at center frequency. It has frequency resolution of 4.8 kHz. The oscillator PN, FOM and FOM<sub>T</sub> at 1-MHz offset frequency from 2.44 GHz carrier frequency are −122.85 dBc/Hz, 196.38 dBc/Hz and 208.19 dBc/Hz, respectively. |
| format | Article |
| id | doaj-art-bd1229ba670144f2bf8ff842ccb2b8d2 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-bd1229ba670144f2bf8ff842ccb2b8d22025-01-30T00:00:54ZengIEEEIEEE Access2169-35362020-01-018972159723010.1109/ACCESS.2020.29958539097205An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCOImran Ali0https://orcid.org/0000-0002-4705-9988Hamed Abbasizadeh1https://orcid.org/0000-0002-3187-534XMuhammad Riaz Ur Rehman2Muhammad Asif3Seong Jin Oh4Young Gun Pu5Minjae Lee6Keum Cheol Hwang7https://orcid.org/0000-0002-8074-1137Youngoo Yang8https://orcid.org/0000-0003-3463-0687Kang-Yoon Lee9https://orcid.org/0000-0001-9777-6953Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USADepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaSchool of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Gwangju, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaIn this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is presented. For locking DCO frequency closest to the target channel, it adaptively controls capacitor banks with binary algorithm. With decrease in frequency resolution, DCO clock counts for each capacitor bank bit evaluation dynamically increases with the proposed technique for accurate frequency tracking. For compensating PVT variations and finding the BLE frequency deviation, the configurable digital DCO gain estimation is incorporated. The low power and constant current DCO operates in sub-threshold region and its power consumption is minimized by <inline-formula> <tex-math notation="LaTeX">$g_{m}/I_{D}$ </tex-math></inline-formula> methodology optimization, constant current source for limiting current in DCO core through adaptive low-dropout regulator (LDO) and lowering the supply voltage. The proposed design is integrated in an ADPLL for BLE transceiver and it is fabricated with 1P6M TSMC 55 nm CMOS technology. The all-digital adaptive FLL is fully synthesizable and its area is <inline-formula> <tex-math notation="LaTeX">$1800~\mu \text{m}^{2}$ </tex-math></inline-formula> with 1.233 K gate count. The RMS current consumption is <inline-formula> <tex-math notation="LaTeX">$103.32~\mu \text{A}$ </tex-math></inline-formula> from 1 V voltage supply with <inline-formula> <tex-math notation="LaTeX">$103.32~\mu \text{W}$ </tex-math></inline-formula> power requirement. The experimental results reveal, DCO draws <inline-formula> <tex-math notation="LaTeX">$480~\mu \text{A}$ </tex-math></inline-formula> current from 0.55 V supply voltage at center frequency. It has frequency resolution of 4.8 kHz. The oscillator PN, FOM and FOM<sub>T</sub> at 1-MHz offset frequency from 2.44 GHz carrier frequency are −122.85 dBc/Hz, 196.38 dBc/Hz and 208.19 dBc/Hz, respectively.https://ieeexplore.ieee.org/document/9097205/Adaptive controllerall-digital frequency locked loopdigitally controlled oscillatorgain estimationconstant currentLDO |
| spellingShingle | Imran Ali Hamed Abbasizadeh Muhammad Riaz Ur Rehman Muhammad Asif Seong Jin Oh Young Gun Pu Minjae Lee Keum Cheol Hwang Youngoo Yang Kang-Yoon Lee An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO IEEE Access Adaptive controller all-digital frequency locked loop digitally controlled oscillator gain estimation constant current LDO |
| title | An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO |
| title_full | An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO |
| title_fullStr | An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO |
| title_full_unstemmed | An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO |
| title_short | An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO |
| title_sort | ultra low power adaptive all digital frequency locked loop with gain estimation and constant current dco |
| topic | Adaptive controller all-digital frequency locked loop digitally controlled oscillator gain estimation constant current LDO |
| url | https://ieeexplore.ieee.org/document/9097205/ |
| work_keys_str_mv | AT imranali anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT hamedabbasizadeh anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT muhammadriazurrehman anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT muhammadasif anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT seongjinoh anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT younggunpu anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT minjaelee anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT keumcheolhwang anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT youngooyang anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT kangyoonlee anultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT imranali ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT hamedabbasizadeh ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT muhammadriazurrehman ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT muhammadasif ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT seongjinoh ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT younggunpu ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT minjaelee ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT keumcheolhwang ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT youngooyang ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco AT kangyoonlee ultralowpoweradaptivealldigitalfrequencylockedloopwithgainestimationandconstantcurrentdco |