12b 500MS/s successive‐approximation‐register‐assisted pipeline analogue‐to‐digital convertor using a four‐stage ring amplifier with coarse‐analogue‐to‐digital convertor embedded
Abstract This article presents a 12b 500MS/s successive‐approximation‐register‐assisted pipeline analogue‐to‐digital converter. By adopting a new auto‐zero scheme, a calibration‐free four‐stage ring residue amplifier with a small offset cancellation capacitor is proposed. In addition, the coarse‐ana...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2024-12-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ell2.70101 |
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