Development of an analog topology for a multi-layer neuronal network

Development of an analog topology for a multi-layer neuronal network

This paper presents a novel approach to implementing artificial neural networks (ANNs) using analog circuits with counter circuits for storing and updating the weights and biases. The counter circuits, which are sequential logic circuits, provide a more precise and stable method for storing and upda...

Full description

Saved in:
Bibliographic Details
Main Authors: Luã da Porciuncula Estrela, Marlon Soares Sigales, Elmer A. Gamboa Peñaloza, Marcelo Lemos Rossi, Mateus Beck Fonseca
Format: Article
Language:English
Published: Elsevier 2025-04-01
Series:Memories - Materials, Devices, Circuits and Systems
Subjects:
Hybrid multiplier
Artificial neural networks
Neuromorphic computing
Online Access:http://www.sciencedirect.com/science/article/pii/S2773064625000052
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a novel approach to implementing artificial neural networks (ANNs) using analog circuits with counter circuits for storing and updating the weights and biases. The counter circuits, which are sequential logic circuits, provide a more precise and stable method for storing and updating the network parameters, compared to memristors. The paper also discusses the design of a multiplier circuit and a hyperbolic function activation circuit used in the neural network. The neural network model based on the XNOR logic function was simulated using a simulation program with integrated circuit emphasis (SPICE), demonstrating its learning capability as the error decreased for each epoch of training. The proposed methodology offers significant advantages for neuromorphic computing, especially in the domain of Internet of Things (IoT), where near-sensor data analysis and edge computation are essential.
ISSN:2773-0646

Similar Items