Low power‐delay‐product dynamic CMOS circuit design techniques

Two low power‐delay‐product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 9...

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Bibliographic Details
Main Authors:	H. Xue, S. Ren
Format:	Article
Language:	English
Published:	Wiley 2017-03-01
Series:	Electronics Letters
Subjects:	PDP dynamic CMOS circuit design techniques low power‐delay‐product circuit design techniques dynamic circuit delay improvement non‐inverted dynamic benchmarks inverted dynamic benchmarks voltage 1.2 V
Online Access:	https://doi.org/10.1049/el.2016.4173
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Low power‐delay‐product dynamic CMOS circuit design techniques

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