Low power‐delay‐product dynamic CMOS circuit design techniques
Two low power‐delay‐product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 9...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2017-03-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/el.2016.4173 |
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| _version_ | 1832096697922093056 |
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| author | H. Xue S. Ren |
| author_facet | H. Xue S. Ren |
| author_sort | H. Xue |
| collection | DOAJ |
| description | Two low power‐delay‐product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed techniques can improve circuit PDP by 19.2 and 61.9% in two non‐inverted dynamic benchmarks, respectively, and 6.2 and 33.72% in two inverted dynamic benchmarks, respectively. |
| format | Article |
| id | doaj-art-b8ff1d05cef4415fa1cecb8e6ed7bd36 |
| institution | Kabale University |
| issn | 0013-5194 1350-911X |
| language | English |
| publishDate | 2017-03-01 |
| publisher | Wiley |
| record_format | Article |
| series | Electronics Letters |
| spelling | doaj-art-b8ff1d05cef4415fa1cecb8e6ed7bd362025-02-05T12:30:42ZengWileyElectronics Letters0013-51941350-911X2017-03-0153530230410.1049/el.2016.4173Low power‐delay‐product dynamic CMOS circuit design techniquesH. Xue0S. Ren1Wright State UniversityDaytonOH45435USAWright State UniversityDaytonOH45435USATwo low power‐delay‐product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed techniques can improve circuit PDP by 19.2 and 61.9% in two non‐inverted dynamic benchmarks, respectively, and 6.2 and 33.72% in two inverted dynamic benchmarks, respectively.https://doi.org/10.1049/el.2016.4173PDP dynamic CMOS circuit design techniqueslow power‐delay‐product circuit design techniquesdynamic circuit delay improvementnon‐inverted dynamic benchmarksinverted dynamic benchmarksvoltage 1.2 V |
| spellingShingle | H. Xue S. Ren Low power‐delay‐product dynamic CMOS circuit design techniques Electronics Letters PDP dynamic CMOS circuit design techniques low power‐delay‐product circuit design techniques dynamic circuit delay improvement non‐inverted dynamic benchmarks inverted dynamic benchmarks voltage 1.2 V |
| title | Low power‐delay‐product dynamic CMOS circuit design techniques |
| title_full | Low power‐delay‐product dynamic CMOS circuit design techniques |
| title_fullStr | Low power‐delay‐product dynamic CMOS circuit design techniques |
| title_full_unstemmed | Low power‐delay‐product dynamic CMOS circuit design techniques |
| title_short | Low power‐delay‐product dynamic CMOS circuit design techniques |
| title_sort | low power delay product dynamic cmos circuit design techniques |
| topic | PDP dynamic CMOS circuit design techniques low power‐delay‐product circuit design techniques dynamic circuit delay improvement non‐inverted dynamic benchmarks inverted dynamic benchmarks voltage 1.2 V |
| url | https://doi.org/10.1049/el.2016.4173 |
| work_keys_str_mv | AT hxue lowpowerdelayproductdynamiccmoscircuitdesigntechniques AT sren lowpowerdelayproductdynamiccmoscircuitdesigntechniques |