Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections
The ever-increasing design complexity of modern digital systems makes it necessary to develop electronic system-level (ESL) methodologies with automation and optimization in the higher abstraction level. How the concurrency is modeled in the application specification plays a significant role in ESL...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
|
| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2012/691864 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832546759418576896 |
|---|---|
| author | Jason Cong Karthik Gururaj Peng Zhang Yi Zou |
| author_facet | Jason Cong Karthik Gururaj Peng Zhang Yi Zou |
| author_sort | Jason Cong |
| collection | DOAJ |
| description | The ever-increasing design complexity of modern digital systems makes it necessary to develop electronic system-level (ESL) methodologies with automation and optimization in the higher abstraction level. How the concurrency is modeled in the application specification plays a significant role in ESL design frameworks. The state-of-art concurrent specification models are not suitable for modeling task-level concurrent behavior for the hardware synthesis design flow. Based on the concurrent collection (CnC) model, which provides the maximum freedom of task rescheduling, we propose task-level data model (TLDM), targeted at the task-level optimization in hardware synthesis for data processing applications. Polyhedral models are embedded in TLDM for concise expression of task instances, array accesses, and dependencies. Examples are shown to illustrate the advantages of our TLDM specification compared to other widely used concurrency specifications. |
| format | Article |
| id | doaj-art-b68f8532b35949f79b1a343a6fa60e42 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-b68f8532b35949f79b1a343a6fa60e422025-02-03T06:47:24ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552012-01-01201210.1155/2012/691864691864Task-Level Data Model for Hardware Synthesis Based on Concurrent CollectionsJason Cong0Karthik Gururaj1Peng Zhang2Yi Zou3Computer Science Department, University of California, Los Angeles, Los Angeles, CA 90095, USAComputer Science Department, University of California, Los Angeles, Los Angeles, CA 90095, USAComputer Science Department, University of California, Los Angeles, Los Angeles, CA 90095, USAComputer Science Department, University of California, Los Angeles, Los Angeles, CA 90095, USAThe ever-increasing design complexity of modern digital systems makes it necessary to develop electronic system-level (ESL) methodologies with automation and optimization in the higher abstraction level. How the concurrency is modeled in the application specification plays a significant role in ESL design frameworks. The state-of-art concurrent specification models are not suitable for modeling task-level concurrent behavior for the hardware synthesis design flow. Based on the concurrent collection (CnC) model, which provides the maximum freedom of task rescheduling, we propose task-level data model (TLDM), targeted at the task-level optimization in hardware synthesis for data processing applications. Polyhedral models are embedded in TLDM for concise expression of task instances, array accesses, and dependencies. Examples are shown to illustrate the advantages of our TLDM specification compared to other widely used concurrency specifications.http://dx.doi.org/10.1155/2012/691864 |
| spellingShingle | Jason Cong Karthik Gururaj Peng Zhang Yi Zou Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections Journal of Electrical and Computer Engineering |
| title | Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections |
| title_full | Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections |
| title_fullStr | Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections |
| title_full_unstemmed | Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections |
| title_short | Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections |
| title_sort | task level data model for hardware synthesis based on concurrent collections |
| url | http://dx.doi.org/10.1155/2012/691864 |
| work_keys_str_mv | AT jasoncong taskleveldatamodelforhardwaresynthesisbasedonconcurrentcollections AT karthikgururaj taskleveldatamodelforhardwaresynthesisbasedonconcurrentcollections AT pengzhang taskleveldatamodelforhardwaresynthesisbasedonconcurrentcollections AT yizou taskleveldatamodelforhardwaresynthesisbasedonconcurrentcollections |