A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance
Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage...
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| Format: | Article |
| Language: | English |
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Wiley
2017-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2017/5419767 |
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| author | David Wilson Aniruddha Shastri Greg Stitt |
| author_facet | David Wilson Aniruddha Shastri Greg Stitt |
| author_sort | David Wilson |
| collection | DOAJ |
| description | Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures. Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x. |
| format | Article |
| id | doaj-art-b1e9633a50b24e55bdc3794c3093831e |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2017-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-b1e9633a50b24e55bdc3794c3093831e2025-02-03T01:31:04ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092017-01-01201710.1155/2017/54197675419767A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault ToleranceDavid Wilson0Aniruddha Shastri1Greg Stitt2Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, USANational Instruments Corp., 11500 N Mopac Expwy, Austin, TX 78759, USADepartment of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, USAComputing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures. Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x.http://dx.doi.org/10.1155/2017/5419767 |
| spellingShingle | David Wilson Aniruddha Shastri Greg Stitt A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance International Journal of Reconfigurable Computing |
| title | A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance |
| title_full | A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance |
| title_fullStr | A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance |
| title_full_unstemmed | A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance |
| title_short | A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance |
| title_sort | high level synthesis scheduling and binding heuristic for fpga fault tolerance |
| url | http://dx.doi.org/10.1155/2017/5419767 |
| work_keys_str_mv | AT davidwilson ahighlevelsynthesisschedulingandbindingheuristicforfpgafaulttolerance AT aniruddhashastri ahighlevelsynthesisschedulingandbindingheuristicforfpgafaulttolerance AT gregstitt ahighlevelsynthesisschedulingandbindingheuristicforfpgafaulttolerance AT davidwilson highlevelsynthesisschedulingandbindingheuristicforfpgafaulttolerance AT aniruddhashastri highlevelsynthesisschedulingandbindingheuristicforfpgafaulttolerance AT gregstitt highlevelsynthesisschedulingandbindingheuristicforfpgafaulttolerance |