APA (7th ed.) Citation

Wilson, D., Shastri, A., & Stitt, G. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. Wiley.

Chicago Style (17th ed.) Citation

Wilson, David, Aniruddha Shastri, and Greg Stitt. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. Wiley.

MLA (9th ed.) Citation

Wilson, David, et al. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. Wiley.