A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator
Abstract The moduli 2n multiplier plays a vital role in the design of a residue number system processor. When the radix‐8 booth‐encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. This paper presents an area and...
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Wiley
2021-01-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12001 |
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| author | Naveen Kr. Kabra Zuber M. Patel |
| author_facet | Naveen Kr. Kabra Zuber M. Patel |
| author_sort | Naveen Kr. Kabra |
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| description | Abstract The moduli 2n multiplier plays a vital role in the design of a residue number system processor. When the radix‐8 booth‐encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. This paper presents an area and power optimization technique for this kind of generators and its implementation in modulo 2n multiplier to improve the performance. The proposed hard multiplier generator (HMG) uses only ⌈log2n⌉‐2 prefix levels and (n−6)⌈log2n⌉−(⌈log2n⌉−1)2⌈log2n⌉2 total prefix operators. The synthesis of the proposed architectures is done using the Cadence tool at Generic Process design Kit‐45 nm technology. The post‐synthesis result of HMG shows 20.27%–36.57%, 2.43%–18.41% saving in area and power, respectively, while the post‐layout result of HMG shows 20.01%–35.26% and 1.33%–29.44% saving in area and power, respectively. The post‐layout result of modulo 2nmultiplier using optimized HMG shows 7.88%–10.04%, 7.87%–12.50%, 3.09%–11.29%, and 3.11%–8.79% saving in area, power, switching energy and Area delay product, respectively. |
| format | Article |
| id | doaj-art-b1b6d78d0ed54cf09049608f94eba939 |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-01-01 |
| publisher | Wiley |
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| series | IET Computers & Digital Techniques |
| spelling | doaj-art-b1b6d78d0ed54cf09049608f94eba9392025-02-03T01:29:37ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-01-01151365510.1049/cdt2.12001A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generatorNaveen Kr. Kabra0Zuber M. Patel1Electronics Engineering Department Sardar Vallabhbhai National Institute of Technology Surat IndiaElectronics Engineering Department Sardar Vallabhbhai National Institute of Technology Surat IndiaAbstract The moduli 2n multiplier plays a vital role in the design of a residue number system processor. When the radix‐8 booth‐encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. This paper presents an area and power optimization technique for this kind of generators and its implementation in modulo 2n multiplier to improve the performance. The proposed hard multiplier generator (HMG) uses only ⌈log2n⌉‐2 prefix levels and (n−6)⌈log2n⌉−(⌈log2n⌉−1)2⌈log2n⌉2 total prefix operators. The synthesis of the proposed architectures is done using the Cadence tool at Generic Process design Kit‐45 nm technology. The post‐synthesis result of HMG shows 20.27%–36.57%, 2.43%–18.41% saving in area and power, respectively, while the post‐layout result of HMG shows 20.01%–35.26% and 1.33%–29.44% saving in area and power, respectively. The post‐layout result of modulo 2nmultiplier using optimized HMG shows 7.88%–10.04%, 7.87%–12.50%, 3.09%–11.29%, and 3.11%–8.79% saving in area, power, switching energy and Area delay product, respectively.https://doi.org/10.1049/cdt2.12001integrated circuit layoutlogic designmicroprocessor chipsmultiplying circuitsresidue number systems |
| spellingShingle | Naveen Kr. Kabra Zuber M. Patel A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator IET Computers & Digital Techniques integrated circuit layout logic design microprocessor chips multiplying circuits residue number systems |
| title | A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator |
| title_full | A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator |
| title_fullStr | A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator |
| title_full_unstemmed | A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator |
| title_short | A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator |
| title_sort | radix 8 modulo 2n multiplier using area and power optimized hard multiple generator |
| topic | integrated circuit layout logic design microprocessor chips multiplying circuits residue number systems |
| url | https://doi.org/10.1049/cdt2.12001 |
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