Modules for Pipelined Mixed Radix FFT Processors
A set of soft IP cores for the Winograd r-point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by r times. Their clock frequency is equal...
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| Format: | Article |
| Language: | English |
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Wiley
2016-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2016/3561317 |
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| author | Anatolij Sergiyenko Anastasia Serhienko |
| author_facet | Anatolij Sergiyenko Anastasia Serhienko |
| author_sort | Anatolij Sergiyenko |
| collection | DOAJ |
| description | A set of soft IP cores for the Winograd r-point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by r times. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA. |
| format | Article |
| id | doaj-art-a90299368ec44a3a92f8c2b1de7d0b29 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2016-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-a90299368ec44a3a92f8c2b1de7d0b292025-02-03T01:22:11ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092016-01-01201610.1155/2016/35613173561317Modules for Pipelined Mixed Radix FFT ProcessorsAnatolij Sergiyenko0Anastasia Serhienko1Computer Science Department, National Technical University of Ukraine, Peremogy Avenue 37, Kiev 03056, UkraineComputer Science Department, National Technical University of Ukraine, Peremogy Avenue 37, Kiev 03056, UkraineA set of soft IP cores for the Winograd r-point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by r times. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.http://dx.doi.org/10.1155/2016/3561317 |
| spellingShingle | Anatolij Sergiyenko Anastasia Serhienko Modules for Pipelined Mixed Radix FFT Processors International Journal of Reconfigurable Computing |
| title | Modules for Pipelined Mixed Radix FFT Processors |
| title_full | Modules for Pipelined Mixed Radix FFT Processors |
| title_fullStr | Modules for Pipelined Mixed Radix FFT Processors |
| title_full_unstemmed | Modules for Pipelined Mixed Radix FFT Processors |
| title_short | Modules for Pipelined Mixed Radix FFT Processors |
| title_sort | modules for pipelined mixed radix fft processors |
| url | http://dx.doi.org/10.1155/2016/3561317 |
| work_keys_str_mv | AT anatolijsergiyenko modulesforpipelinedmixedradixfftprocessors AT anastasiaserhienko modulesforpipelinedmixedradixfftprocessors |