Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication
Abstract Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as...
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| Format: | Article |
| Language: | English |
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Wiley
2021-08-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12041 |
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| author | Geetam Singh Tomar Marcus Llyode George Abhineet Singh Tomar |
| author_facet | Geetam Singh Tomar Marcus Llyode George Abhineet Singh Tomar |
| author_sort | Geetam Singh Tomar |
| collection | DOAJ |
| description | Abstract Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating‐point multiplication is an important component. The dynamic range of numbers represented by floating‐point arithmetic is very large compared with that of fixed‐point numbers of the same bit width. A mantissa similarity investigator (MSI)–interfaced multi‐precision binary multiplier architecture is developed and can be used in data‐intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single‐, double‐, quadruple‐ and octuple‐precision modes for mantissa multiplication according to the IEEE 754 standard for floating‐point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field‐programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator. |
| format | Article |
| id | doaj-art-a815ffe4ba8e4caf9436ca85e8fa7cd4 |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-08-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-a815ffe4ba8e4caf9436ca85e8fa7cd42025-02-03T06:47:28ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-08-0115545546410.1049/cds2.12041Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplicationGeetam Singh Tomar0Marcus Llyode George1Abhineet Singh Tomar2Rajkiya Engineering College Sonbhadra IndiaDepartment of Electrical and Computer Engineering University of West Indies St. Augustine Trinidad and TobagoVolvo Group Trucks Technology Gothenburg SwedenAbstract Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating‐point multiplication is an important component. The dynamic range of numbers represented by floating‐point arithmetic is very large compared with that of fixed‐point numbers of the same bit width. A mantissa similarity investigator (MSI)–interfaced multi‐precision binary multiplier architecture is developed and can be used in data‐intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single‐, double‐, quadruple‐ and octuple‐precision modes for mantissa multiplication according to the IEEE 754 standard for floating‐point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field‐programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator.https://doi.org/10.1049/cds2.12041field programmable gate arraysfloating point arithmeticlogic designmultiplying circuits |
| spellingShingle | Geetam Singh Tomar Marcus Llyode George Abhineet Singh Tomar Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication IET Circuits, Devices and Systems field programmable gate arrays floating point arithmetic logic design multiplying circuits |
| title | Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication |
| title_full | Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication |
| title_fullStr | Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication |
| title_full_unstemmed | Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication |
| title_short | Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication |
| title_sort | multi precision binary multiplier architecture for multi precision floating point multiplication |
| topic | field programmable gate arrays floating point arithmetic logic design multiplying circuits |
| url | https://doi.org/10.1049/cds2.12041 |
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