A 500MS/s 14-bit Pipelined ADC With Startup Protection Circuit in 40 nm CMOS
This paper presents a 500 MS/s 14-bit pipelined analog-to-digital converter (ADC) implemented in a 40 nm CMOS process. During power-up, the system is initially unstable, and the terminal voltage of certain transistors may exceed their specified breakdown voltage, putting them at risk of damage. To a...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10915601/ |
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| Summary: | This paper presents a 500 MS/s 14-bit pipelined analog-to-digital converter (ADC) implemented in a 40 nm CMOS process. During power-up, the system is initially unstable, and the terminal voltage of certain transistors may exceed their specified breakdown voltage, putting them at risk of damage. To address this issue, we propose an input buffer and an operational amplifier, each equipped with a startup protection circuit, effectively mitigating these risks without significantly impacting system performance. To improve front-end nonlinearity and inter-stage gain errors caused by the finite gain of the operational amplifier and capacitance mismatches, we implement calibration dither and linearization dither techniques. The measurement results show that injecting dither improves the signal-to-noise distortion ratio (SNDR), increasing it from 64.3 dB to 70 dB, while the spurious-free dynamic range (SFDR) rises from 68.5 dB to 88.5 dB. Notably, the SFDR remains as high as 85.5 dB for input frequencies up to the Nyquist rate. |
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| ISSN: | 2169-3536 |