Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With ΔΣ Quantization Cancellation
A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7). While fractional-N phase-locked loops (PLLs) and...
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10707313/ |
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| author | Yizhe Hu Weichen Tao Robert Bogdan Staszewski |
| author_facet | Yizhe Hu Weichen Tao Robert Bogdan Staszewski |
| author_sort | Yizhe Hu |
| collection | DOAJ |
| description | A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7). While fractional-N phase-locked loops (PLLs) and injection-locking techniques with delta–sigma <inline-formula> <tex-math notation="LaTeX">$(\Delta \Sigma )$ </tex-math></inline-formula> quantization cancellation using a digital-to-time converter (DTC) (and more recently, DACs) have demonstrated low-jitter performance and are well understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this article, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a first- or second-order <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness. |
| format | Article |
| id | doaj-art-9f472b62428147c1908ca680cd346197 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-9f472b62428147c1908ca680cd3461972025-01-25T00:03:08ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01422623710.1109/OJSSCS.2024.347603510707313Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With ΔΣ Quantization CancellationYizhe Hu0https://orcid.org/0000-0003-3685-7666Weichen Tao1https://orcid.org/0009-0007-3769-8181Robert Bogdan Staszewski2https://orcid.org/0000-0001-9848-1129School of Microelectronics, University of Science and Technology of China, Hefei, ChinaSchool of Microelectronics, University of Science and Technology of China, Hefei, ChinaSchool of Electrical and Electronic Engineering, University College Dublin, Dublin 4, IrelandA fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7). While fractional-N phase-locked loops (PLLs) and injection-locking techniques with delta–sigma <inline-formula> <tex-math notation="LaTeX">$(\Delta \Sigma )$ </tex-math></inline-formula> quantization cancellation using a digital-to-time converter (DTC) (and more recently, DACs) have demonstrated low-jitter performance and are well understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this article, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a first- or second-order <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness.https://ieeexplore.ieee.org/document/10707313/All-digital phase-locked loop (ADPLL)delta–sigma modulator (DSM)digital-to-time converter (DTC)fractional-Nintegral nonlinearity (INL)millimeter-wave (mmWave) |
| spellingShingle | Yizhe Hu Weichen Tao Robert Bogdan Staszewski Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With ΔΣ Quantization Cancellation IEEE Open Journal of the Solid-State Circuits Society All-digital phase-locked loop (ADPLL) delta–sigma modulator (DSM) digital-to-time converter (DTC) fractional-N integral nonlinearity (INL) millimeter-wave (mmWave) |
| title | Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With ΔΣ Quantization Cancellation |
| title_full | Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With ΔΣ Quantization Cancellation |
| title_fullStr | Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With ΔΣ Quantization Cancellation |
| title_full_unstemmed | Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With ΔΣ Quantization Cancellation |
| title_short | Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With ΔΣ Quantization Cancellation |
| title_sort | nonlinearity induced spur analysis in fractional italic n italic synthesizers with x0394 x03a3 quantization cancellation |
| topic | All-digital phase-locked loop (ADPLL) delta–sigma modulator (DSM) digital-to-time converter (DTC) fractional-N integral nonlinearity (INL) millimeter-wave (mmWave) |
| url | https://ieeexplore.ieee.org/document/10707313/ |
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