TSC-IBR: A Variant of Interval-Based Memory Reclamation Using CPU’s Time-Stamp Counter
Hardware timestamps are increasingly used in concurrent data structures. On the x86_64 platform, a clock with cycle-level resolution maintained by the CPU’s time-stamp counter register is frequently employed to implement parallel algorithms, and its value can be accessed swiftly without a...
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IEEE
2025-01-01
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| Online Access: | https://ieeexplore.ieee.org/document/11000280/ |
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| author | Chen Zhang Wendong Li Xinghui Zhu |
| author_facet | Chen Zhang Wendong Li Xinghui Zhu |
| author_sort | Chen Zhang |
| collection | DOAJ |
| description | Hardware timestamps are increasingly used in concurrent data structures. On the x86_64 platform, a clock with cycle-level resolution maintained by the CPU’s time-stamp counter register is frequently employed to implement parallel algorithms, and its value can be accessed swiftly without a system call. In line with this emerging trend, our research focuses on leveraging the CPU’s time-stamp counter in a memory management algorithm to secure safe memory reclamation in concurrent data structures. Existing quiescent-state-based memory reclamation algorithms rely on a global epoch counter maintained via a software timestamp. Although most quiescent-state-based methods demonstrate good performance when employed in lock-free concurrent data structures, they grapple with issues concerning robustness. Specifically, in Interval-Based Reclamation, a thread reclaiming a shared memory block must check whether the lifetime of the block intersects with the reserved epoch intervals of all threads. Interval-Based Reclamation can provide more fine-grained memory management than Epoch-Based Reclamation and hazard eras. In this study, we propose TSC-IBR, a variant of Interval-Based Reclamation. TSC-IBR leverages the CPU’s timestamp counter instead of the software timestamp. Our experiments confirmed the practicability of employing the CPU’s time-stamp counter in a memory reclamation algorithm. Compared to other quiescent-state-based methods using the software timestamp, TSC-IBR exhibits excellent robustness across all our lock-free concurrent data structure benchmarks and attains high throughput in most cases. |
| format | Article |
| id | doaj-art-9dd5be5d22eb4c00bc7c3e84936c585f |
| institution | DOAJ |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-9dd5be5d22eb4c00bc7c3e84936c585f2025-08-20T03:12:46ZengIEEEIEEE Access2169-35362025-01-0113902009021110.1109/ACCESS.2025.356907211000280TSC-IBR: A Variant of Interval-Based Memory Reclamation Using CPU’s Time-Stamp CounterChen Zhang0https://orcid.org/0009-0003-3000-3261Wendong Li1Xinghui Zhu2https://orcid.org/0000-0002-7150-0008College of Information and Intelligence, Hunan Agricultural University, Changsha, ChinaCollege of Information and Intelligence, Hunan Agricultural University, Changsha, ChinaCollege of Information and Intelligence, Hunan Agricultural University, Changsha, ChinaHardware timestamps are increasingly used in concurrent data structures. On the x86_64 platform, a clock with cycle-level resolution maintained by the CPU’s time-stamp counter register is frequently employed to implement parallel algorithms, and its value can be accessed swiftly without a system call. In line with this emerging trend, our research focuses on leveraging the CPU’s time-stamp counter in a memory management algorithm to secure safe memory reclamation in concurrent data structures. Existing quiescent-state-based memory reclamation algorithms rely on a global epoch counter maintained via a software timestamp. Although most quiescent-state-based methods demonstrate good performance when employed in lock-free concurrent data structures, they grapple with issues concerning robustness. Specifically, in Interval-Based Reclamation, a thread reclaiming a shared memory block must check whether the lifetime of the block intersects with the reserved epoch intervals of all threads. Interval-Based Reclamation can provide more fine-grained memory management than Epoch-Based Reclamation and hazard eras. In this study, we propose TSC-IBR, a variant of Interval-Based Reclamation. TSC-IBR leverages the CPU’s timestamp counter instead of the software timestamp. Our experiments confirmed the practicability of employing the CPU’s time-stamp counter in a memory reclamation algorithm. Compared to other quiescent-state-based methods using the software timestamp, TSC-IBR exhibits excellent robustness across all our lock-free concurrent data structure benchmarks and attains high throughput in most cases.https://ieeexplore.ieee.org/document/11000280/CPU’s time-stamp countersafe memory reclamationconcurrent data structuresshared memorygarbage collectionparallel algorithms |
| spellingShingle | Chen Zhang Wendong Li Xinghui Zhu TSC-IBR: A Variant of Interval-Based Memory Reclamation Using CPU’s Time-Stamp Counter IEEE Access CPU’s time-stamp counter safe memory reclamation concurrent data structures shared memory garbage collection parallel algorithms |
| title | TSC-IBR: A Variant of Interval-Based Memory Reclamation Using CPU’s Time-Stamp Counter |
| title_full | TSC-IBR: A Variant of Interval-Based Memory Reclamation Using CPU’s Time-Stamp Counter |
| title_fullStr | TSC-IBR: A Variant of Interval-Based Memory Reclamation Using CPU’s Time-Stamp Counter |
| title_full_unstemmed | TSC-IBR: A Variant of Interval-Based Memory Reclamation Using CPU’s Time-Stamp Counter |
| title_short | TSC-IBR: A Variant of Interval-Based Memory Reclamation Using CPU’s Time-Stamp Counter |
| title_sort | tsc ibr a variant of interval based memory reclamation using cpu x2019 s time stamp counter |
| topic | CPU’s time-stamp counter safe memory reclamation concurrent data structures shared memory garbage collection parallel algorithms |
| url | https://ieeexplore.ieee.org/document/11000280/ |
| work_keys_str_mv | AT chenzhang tscibravariantofintervalbasedmemoryreclamationusingcpux2019stimestampcounter AT wendongli tscibravariantofintervalbasedmemoryreclamationusingcpux2019stimestampcounter AT xinghuizhu tscibravariantofintervalbasedmemoryreclamationusingcpux2019stimestampcounter |