TVD‐PB logic circuit based on camouflaging circuit for IoT security
Abstract Internet of Things (IoT) devices are vulnerable to many physical attacks, including reverse engineering and side‐channel analysis because the sensitive information of circuits may be leaked through the physical characteristics of the device. A logic camouflaging circuit is proposed that use...
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| Format: | Article |
| Language: | English |
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Wiley
2022-01-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12080 |
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| _version_ | 1832546823828406272 |
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| author | Yuejun Zhang Qiufeng Wu Pengjun Wang Liang Wen Zhicun Luan Chongyan Gu |
| author_facet | Yuejun Zhang Qiufeng Wu Pengjun Wang Liang Wen Zhicun Luan Chongyan Gu |
| author_sort | Yuejun Zhang |
| collection | DOAJ |
| description | Abstract Internet of Things (IoT) devices are vulnerable to many physical attacks, including reverse engineering and side‐channel analysis because the sensitive information of circuits may be leaked through the physical characteristics of the device. A logic camouflaging circuit is proposed that uses a balanced power consumption and threshold voltage‐defined technique to provide an antiphysical attack scheme to protect the hardware security for IoT devices. The proposed circuit uses a symmetric differential pull‐down network in implementing the different logic functions through the threshold voltage reconfiguration circuit. As a result, the power consumption of the circuit attains balance and stability between two different logical operations. The proposed threshold voltage‐defined power‐balance (TVD‐PB) design is fabricated using a 65‐nm CMOS technology, and the core area occupies approximately 0.0044 mm2, composed of NAND, NOR, XOR, and INV components and multiplier gates of the proposed TVD‐PB circuit. The entire chip passed the logic function tests. The measured results show that the average similarity of the TVD‐PB universal gate is 99.68%. In addition, the current margin is higher than 55 μA and power consumption of 0.455 mW during each clock cycle at 1.2 V derives 0.1072% of the normalized energy deviation and 0.0453% of the normalized standard deviation. Compared with other state‐of‐the‐art techniques, the power dependency against power attacks is improved effectively. |
| format | Article |
| id | doaj-art-9b912e78000f401086b61bdc0df69798 |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2022-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-9b912e78000f401086b61bdc0df697982025-02-03T06:47:11ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982022-01-01161405210.1049/cds2.12080TVD‐PB logic circuit based on camouflaging circuit for IoT securityYuejun Zhang0Qiufeng Wu1Pengjun Wang2Liang Wen3Zhicun Luan4Chongyan Gu5Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo Zhejiang ChinaFaculty of Electrical Engineering and Computer Science Ningbo University Ningbo Zhejiang ChinaCollege of Electrical and Electronic Engineering Wenzhou University Wenzhou ChinaDepartment of Electronic Technology China Coast Guard Academy Ningbo Zhejiang ChinaFaculty of Electrical Engineering and Computer Science Ningbo University Ningbo Zhejiang ChinaCentre for Secure Information Technologies Institute of Electronics, Communications, and Information Technology Queen's University Belfast Belfast UKAbstract Internet of Things (IoT) devices are vulnerable to many physical attacks, including reverse engineering and side‐channel analysis because the sensitive information of circuits may be leaked through the physical characteristics of the device. A logic camouflaging circuit is proposed that uses a balanced power consumption and threshold voltage‐defined technique to provide an antiphysical attack scheme to protect the hardware security for IoT devices. The proposed circuit uses a symmetric differential pull‐down network in implementing the different logic functions through the threshold voltage reconfiguration circuit. As a result, the power consumption of the circuit attains balance and stability between two different logical operations. The proposed threshold voltage‐defined power‐balance (TVD‐PB) design is fabricated using a 65‐nm CMOS technology, and the core area occupies approximately 0.0044 mm2, composed of NAND, NOR, XOR, and INV components and multiplier gates of the proposed TVD‐PB circuit. The entire chip passed the logic function tests. The measured results show that the average similarity of the TVD‐PB universal gate is 99.68%. In addition, the current margin is higher than 55 μA and power consumption of 0.455 mW during each clock cycle at 1.2 V derives 0.1072% of the normalized energy deviation and 0.0453% of the normalized standard deviation. Compared with other state‐of‐the‐art techniques, the power dependency against power attacks is improved effectively.https://doi.org/10.1049/cds2.12080logic gatesintegrated circuit designpower consumptionCMOS logic circuitsInternet of Thingslogic design |
| spellingShingle | Yuejun Zhang Qiufeng Wu Pengjun Wang Liang Wen Zhicun Luan Chongyan Gu TVD‐PB logic circuit based on camouflaging circuit for IoT security IET Circuits, Devices and Systems logic gates integrated circuit design power consumption CMOS logic circuits Internet of Things logic design |
| title | TVD‐PB logic circuit based on camouflaging circuit for IoT security |
| title_full | TVD‐PB logic circuit based on camouflaging circuit for IoT security |
| title_fullStr | TVD‐PB logic circuit based on camouflaging circuit for IoT security |
| title_full_unstemmed | TVD‐PB logic circuit based on camouflaging circuit for IoT security |
| title_short | TVD‐PB logic circuit based on camouflaging circuit for IoT security |
| title_sort | tvd pb logic circuit based on camouflaging circuit for iot security |
| topic | logic gates integrated circuit design power consumption CMOS logic circuits Internet of Things logic design |
| url | https://doi.org/10.1049/cds2.12080 |
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