Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection
In this paper, the design and the implementation of a pipelined hardware accelerator based on a fuzzy logic approach for an edge detection system are presented. The fuzzy system comprises a preprocessing stage, a fuzzifier with four fuzzy inputs, an inference system with seven rules, and a defuzzifi...
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| Format: | Article |
| Language: | English |
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Wiley
2017-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2017/1325493 |
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| author | Aous H. Kurdi Janos L. Grantner Ikhlas M. Abdel-Qader |
| author_facet | Aous H. Kurdi Janos L. Grantner Ikhlas M. Abdel-Qader |
| author_sort | Aous H. Kurdi |
| collection | DOAJ |
| description | In this paper, the design and the implementation of a pipelined hardware accelerator based on a fuzzy logic approach for an edge detection system are presented. The fuzzy system comprises a preprocessing stage, a fuzzifier with four fuzzy inputs, an inference system with seven rules, and a defuzzification stage delivering a single crisp output, which represents the intensity value of a pixel in the output image. The hardware accelerator consists of seven stages with one clock cycle latency per stage. The defuzzification stage was implemented using three different defuzzification methods. These methods are the mean of maxima, the smallest of maxima, and the largest of maxima. The defuzzification modules are interchangeable while the system runs using partial reconfiguration design methodology. System development was carried out using Vivado High-Level Synthesis, Vivado Design Suite, Vivado Simulator, and a set of Xilinx 7000 FPGA devices. Depending upon the speed grade of the device that is employed, the system can operate at a frequency range from 83 MHz to 125 MHz. Its peak performance is up to 58 high definition frames per second. A comparison of this system’s performance and its software counterpart shows a significant speedup in the magnitude of hundred thousand times. |
| format | Article |
| id | doaj-art-9a2d302a6cfe4771ad67c88a2ec118f6 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2017-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-9a2d302a6cfe4771ad67c88a2ec118f62025-02-03T01:11:27ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092017-01-01201710.1155/2017/13254931325493Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge DetectionAous H. Kurdi0Janos L. Grantner1Ikhlas M. Abdel-Qader2Electrical and Computer Engineering Department, Western Michigan University, Kalamazoo, MI 49009, USAElectrical and Computer Engineering Department, Western Michigan University, Kalamazoo, MI 49009, USAElectrical and Computer Engineering Department, Western Michigan University, Kalamazoo, MI 49009, USAIn this paper, the design and the implementation of a pipelined hardware accelerator based on a fuzzy logic approach for an edge detection system are presented. The fuzzy system comprises a preprocessing stage, a fuzzifier with four fuzzy inputs, an inference system with seven rules, and a defuzzification stage delivering a single crisp output, which represents the intensity value of a pixel in the output image. The hardware accelerator consists of seven stages with one clock cycle latency per stage. The defuzzification stage was implemented using three different defuzzification methods. These methods are the mean of maxima, the smallest of maxima, and the largest of maxima. The defuzzification modules are interchangeable while the system runs using partial reconfiguration design methodology. System development was carried out using Vivado High-Level Synthesis, Vivado Design Suite, Vivado Simulator, and a set of Xilinx 7000 FPGA devices. Depending upon the speed grade of the device that is employed, the system can operate at a frequency range from 83 MHz to 125 MHz. Its peak performance is up to 58 high definition frames per second. A comparison of this system’s performance and its software counterpart shows a significant speedup in the magnitude of hundred thousand times.http://dx.doi.org/10.1155/2017/1325493 |
| spellingShingle | Aous H. Kurdi Janos L. Grantner Ikhlas M. Abdel-Qader Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection International Journal of Reconfigurable Computing |
| title | Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection |
| title_full | Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection |
| title_fullStr | Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection |
| title_full_unstemmed | Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection |
| title_short | Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection |
| title_sort | fuzzy logic based hardware accelerator with partially reconfigurable defuzzification stage for image edge detection |
| url | http://dx.doi.org/10.1155/2017/1325493 |
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