Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology
A 10‐bit pipelined analogue‐to‐digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal–oxide–semiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) n‐well technology. The internal gain of value 2 of the intermediate st...
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Wiley
2017-11-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/iet-cds.2016.0525 |
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| author | Anil Singh Veena Rawat Alpana Agarwal |
| author_facet | Anil Singh Veena Rawat Alpana Agarwal |
| author_sort | Anil Singh |
| collection | DOAJ |
| description | A 10‐bit pipelined analogue‐to‐digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal–oxide–semiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) n‐well technology. The internal gain of value 2 of the intermediate stages is achieved by using a charge‐pump‐based concept that avoids the use of power‐area inefficient operational amplifier. All the capacitors are realised by capacitors implemented by metal–oxide–semiconductor field‐effect transistors (MOSCAPs) that allows easy integration with any inexpensive standard digital CMOS technology, and altogether giving low area‐power‐cost solution. A low DC gain CMOS differential amplifier in source follower configuration is used and low gain effects are calibrated digitally in the background. Peak differential non‐linearity (DNL) improves from −1/+0.27 least significant bit (LSB) to −0.43/+0.57 LSB and peak integral non‐linearity (INL) is reduced from −9.56/+9.3 LSB to within range of ±0.5 LSB after calibration. Also signal‐to‐noise plus distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) increase to 65.4 and 72.08 dB, respectively, after calibration. |
| format | Article |
| id | doaj-art-98f9e2fb614f4adb9abf5febac2b1c23 |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2017-11-01 |
| publisher | Wiley |
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| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-98f9e2fb614f4adb9abf5febac2b1c232025-02-03T01:32:08ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982017-11-0111658959610.1049/iet-cds.2016.0525Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technologyAnil Singh0Veena Rawat1Alpana Agarwal2Electronics and Communication Engineering DepartmentThapar UniversityPatialaIndiaPESCOChandigarhIndiaElectronics and Communication Engineering DepartmentThapar UniversityPatialaIndiaA 10‐bit pipelined analogue‐to‐digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal–oxide–semiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) n‐well technology. The internal gain of value 2 of the intermediate stages is achieved by using a charge‐pump‐based concept that avoids the use of power‐area inefficient operational amplifier. All the capacitors are realised by capacitors implemented by metal–oxide–semiconductor field‐effect transistors (MOSCAPs) that allows easy integration with any inexpensive standard digital CMOS technology, and altogether giving low area‐power‐cost solution. A low DC gain CMOS differential amplifier in source follower configuration is used and low gain effects are calibrated digitally in the background. Peak differential non‐linearity (DNL) improves from −1/+0.27 least significant bit (LSB) to −0.43/+0.57 LSB and peak integral non‐linearity (INL) is reduced from −9.56/+9.3 LSB to within range of ±0.5 LSB after calibration. Also signal‐to‐noise plus distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) increase to 65.4 and 72.08 dB, respectively, after calibration.https://doi.org/10.1049/iet-cds.2016.0525low-power pipelined ADCdigital CMOS technologypipelined analogue-to-digital convertermetal-oxide-semiconductor transistorsMOS transistorsstandard digital complementary n-well technology |
| spellingShingle | Anil Singh Veena Rawat Alpana Agarwal Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology IET Circuits, Devices and Systems low-power pipelined ADC digital CMOS technology pipelined analogue-to-digital converter metal-oxide-semiconductor transistors MOS transistors standard digital complementary n-well technology |
| title | Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology |
| title_full | Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology |
| title_fullStr | Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology |
| title_full_unstemmed | Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology |
| title_short | Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology |
| title_sort | low power 10 bit 100 ms s pipelined adc in digital cmos technology |
| topic | low-power pipelined ADC digital CMOS technology pipelined analogue-to-digital converter metal-oxide-semiconductor transistors MOS transistors standard digital complementary n-well technology |
| url | https://doi.org/10.1049/iet-cds.2016.0525 |
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