NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution
Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as Runahead and out-of-order execution that require nonblocking caches to tolera...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2012/915178 |
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| Summary: | Soft processors often use data caches to reduce the gap between processor and
main memory speeds. To achieve high efficiency, simple, blocking caches are used.
Such caches are not appropriate for processor designs such as Runahead and out-of-order execution that require nonblocking caches to tolerate main memory latencies.
Instead, these processors use non-blocking caches to extract memory level parallelism
and improve performance. However, conventional non-blocking cache designs are expensive and slow on FPGAs as they use content-addressable memories (CAMs). This
work proposes NCOR, an FPGA-friendly non-blocking cache that exploits the key
properties of Runahead execution. NCOR does not require CAMs and utilizes smart
cache controllers. A 4 KB NCOR operates at 329 MHz on Stratix III FPGAs while it
uses only 270 logic elements. A 32 KB NCOR operates at 278 Mhz and uses 269 logic
elements. |
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| ISSN: | 1687-7195 1687-7209 |