Low-Power and High-Performance Double-Node-Upset-Tolerant Latch Using Input-Splitting C-Element
Data accuracy is critical for sensor systems. As essential components of digital circuits within sensor systems, nanoscale CMOS latches are particularly susceptible to single-node upsets (SNUs) and double-node upsets (DNUs), which can lead to data errors. In this paper, a highly robust Double-Node-U...
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2025-04-01
|
| Series: | Sensors |
| Subjects: | |
| Online Access: | https://www.mdpi.com/1424-8220/25/8/2435 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|