A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications
A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse-grained processing elements that can be configured as complex DSP functions that are the basic building bloc...
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| Format: | Article |
| Language: | English |
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Wiley
2009-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2009/529512 |
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| author | H. Ho V. Szwarc T. Kwasniewski |
| author_facet | H. Ho V. Szwarc T. Kwasniewski |
| author_sort | H. Ho |
| collection | DOAJ |
| description | A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse-grained processing elements that can be configured as complex DSP functions that are the basic building blocks of Polyphase-FIR filters, phase shifters, DFTs, and Polyphase-DFT circuits. The homogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to its nearest neighbors via configurable switch (SW) elements, enables array expansion for parallel processing and facilitates time
sharing computation of high-throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimization technique has been employed to reduce the overall number of vector-matrix products to be mapped on the RSA. The hardware complexity and throughput of the RSA-based DFT structures have been evaluated and compared against several conventional modular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphase filter circuits are also presented. The RSA architecture offers significant flexibility and computational capacity for applications that require real time reconfiguration and high-density computing. |
| format | Article |
| id | doaj-art-963e568ab83b4a188fecf84f24ee28b3 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2009-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-963e568ab83b4a188fecf84f24ee28b32025-02-03T05:44:24ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092009-01-01200910.1155/2009/529512529512A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate ApplicationsH. Ho0V. Szwarc1T. Kwasniewski2Terrestrial Wireless Systems, Communications Research Centre, 3701 Carling Avenue, BOX 11490, Station H, Ottawa, ON, K2H 8S2, CanadaTerrestrial Wireless Systems, Communications Research Centre, 3701 Carling Avenue, BOX 11490, Station H, Ottawa, ON, K2H 8S2, CanadaDepartment of Electronics, Carleton University, 1125 Colonel By Drive, Ottawa, ON, K1S 5B6, CanadaA reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse-grained processing elements that can be configured as complex DSP functions that are the basic building blocks of Polyphase-FIR filters, phase shifters, DFTs, and Polyphase-DFT circuits. The homogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to its nearest neighbors via configurable switch (SW) elements, enables array expansion for parallel processing and facilitates time sharing computation of high-throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimization technique has been employed to reduce the overall number of vector-matrix products to be mapped on the RSA. The hardware complexity and throughput of the RSA-based DFT structures have been evaluated and compared against several conventional modular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphase filter circuits are also presented. The RSA architecture offers significant flexibility and computational capacity for applications that require real time reconfiguration and high-density computing.http://dx.doi.org/10.1155/2009/529512 |
| spellingShingle | H. Ho V. Szwarc T. Kwasniewski A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications International Journal of Reconfigurable Computing |
| title | A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications |
| title_full | A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications |
| title_fullStr | A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications |
| title_full_unstemmed | A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications |
| title_short | A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications |
| title_sort | reconfigurable systolic array architecture for multicarrier wireless and multirate applications |
| url | http://dx.doi.org/10.1155/2009/529512 |
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