Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization
Abstract This paper proposes an efficient high‐order finite impulse response (FIR) filter structure for field programmable gate array (FPGA)‐based applications with simultaneous digital signal processing (DSP) and look‐up‐table (LUT) reduced utilization. The real‐time updating of the filter coeffici...
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| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-08-01
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| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12043 |
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