APA (7th ed.) Citation

Maamoun, M., Hassani, A., Dahmani, S., Saadi, H. A., Zerari, G., Chabini, N., & Beguenane, R. Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization. Wiley.

Chicago Style (17th ed.) Citation

Maamoun, Mountassar, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, and Rachid Beguenane. Efficient FPGA Based Architecture for High‐order FIR Filtering Using Simultaneous DSP and LUT Reduced Utilization. Wiley.

MLA (9th ed.) Citation

Maamoun, Mountassar, et al. Efficient FPGA Based Architecture for High‐order FIR Filtering Using Simultaneous DSP and LUT Reduced Utilization. Wiley.