A novel buffering fault‐tolerance approach for network on chip (NoC)
Abstract Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against fail...
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| Format: | Article |
| Language: | English |
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Wiley
2023-07-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12127 |
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| author | Nima Jafarzadeh Ahmad Jalili Jafar A. Alzubi Khosro Rezaee Yang Liu Mehdi Gheisari Bahram Sadeghi Bigham Amir Javadpour |
| author_facet | Nima Jafarzadeh Ahmad Jalili Jafar A. Alzubi Khosro Rezaee Yang Liu Mehdi Gheisari Bahram Sadeghi Bigham Amir Javadpour |
| author_sort | Nima Jafarzadeh |
| collection | DOAJ |
| description | Abstract Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance is proposed, which uses the existing resources efficiently. So, it does not impose any overhead on hardware and improves the error tolerance scale. The authors also evaluate it from different perspectives to show its superior performance. |
| format | Article |
| id | doaj-art-95fa5902782b4ed5a31f4e2bd55413ff |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2023-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-95fa5902782b4ed5a31f4e2bd55413ff2025-02-03T06:45:05ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982023-07-0117425025710.1049/cds2.12127A novel buffering fault‐tolerance approach for network on chip (NoC)Nima Jafarzadeh0Ahmad Jalili1Jafar A. Alzubi2Khosro Rezaee3Yang Liu4Mehdi Gheisari5Bahram Sadeghi Bigham6Amir Javadpour7Department of Computer Engineering Islamic Azad University, South Tehran Branch Tehran IranDepartment of Computer Engineering, Faculty of Basic Sciences and Engineering Gonbad Kavous University Gonbad Kavous IranFaculty of Engineering Al‐Balqa Applied University Salt JordanDepartment of Biomedical Engineering Meybod University Meybod IranDepartment of Computer Science and Technology Harbin Institute of Technology Shenzhen ChinaDepartment of Computer Science Islamic Azad University Damavand IranDepartment of Computer Science, Faculty of Mathematical Sciences Alzahra University Tehran IranDepartment of Computer Science and Technology Harbin Institute of Technology Shenzhen ChinaAbstract Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance is proposed, which uses the existing resources efficiently. So, it does not impose any overhead on hardware and improves the error tolerance scale. The authors also evaluate it from different perspectives to show its superior performance.https://doi.org/10.1049/cds2.12127fault toleranceintegrated circuit reliabilitymicroprocessor chipsnetwork‐on‐chip |
| spellingShingle | Nima Jafarzadeh Ahmad Jalili Jafar A. Alzubi Khosro Rezaee Yang Liu Mehdi Gheisari Bahram Sadeghi Bigham Amir Javadpour A novel buffering fault‐tolerance approach for network on chip (NoC) IET Circuits, Devices and Systems fault tolerance integrated circuit reliability microprocessor chips network‐on‐chip |
| title | A novel buffering fault‐tolerance approach for network on chip (NoC) |
| title_full | A novel buffering fault‐tolerance approach for network on chip (NoC) |
| title_fullStr | A novel buffering fault‐tolerance approach for network on chip (NoC) |
| title_full_unstemmed | A novel buffering fault‐tolerance approach for network on chip (NoC) |
| title_short | A novel buffering fault‐tolerance approach for network on chip (NoC) |
| title_sort | novel buffering fault tolerance approach for network on chip noc |
| topic | fault tolerance integrated circuit reliability microprocessor chips network‐on‐chip |
| url | https://doi.org/10.1049/cds2.12127 |
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