Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter
In this paper, a novel p-type junctionless field effect transistor (PJLFET) based on a partially depleted silicon-on-insulator (PD-SOI) is proposed and investigated. The novel PJLFET integrates a buried N+-doped layer under the channel to enable the device to be turned off, leading to a special work...
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| Language: | English |
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MDPI AG
2025-01-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/16/1/106 |
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| author | Bin Wang Ziyuan Tang Yuxiang Song Lu Liu Weitao Yang Longsheng Wu |
| author_facet | Bin Wang Ziyuan Tang Yuxiang Song Lu Liu Weitao Yang Longsheng Wu |
| author_sort | Bin Wang |
| collection | DOAJ |
| description | In this paper, a novel p-type junctionless field effect transistor (PJLFET) based on a partially depleted silicon-on-insulator (PD-SOI) is proposed and investigated. The novel PJLFET integrates a buried N+-doped layer under the channel to enable the device to be turned off, leading to a special work mechanism and optimized performance. Simulation results show that the proposed PJLFET demonstrates an I<sub>on</sub>/I<sub>off</sub> ratio of more than seven orders of magnitude, with I<sub>on</sub> reaching up to 2.56 × 10<sup>−4</sup> A/μm, I<sub>off</sub> as low as 3.99 × 10<sup>−12</sup> A/μm, and a threshold voltage reduced to −0.43 V, exhibiting excellent electrical characteristics. Furthermore, a new CMOS inverter comprising a proposed PJLFET and a conventional NMOSFET is designed. With the identical geometric dimensions and gate electrode, the pull-up and pull-down driving capabilities of the proposed CMOS are equivalent, showing the potential for application in high-performance chips in the future. |
| format | Article |
| id | doaj-art-94cd2d52820344c0859e5432c2ef059d |
| institution | Kabale University |
| issn | 2072-666X |
| language | English |
| publishDate | 2025-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj-art-94cd2d52820344c0859e5432c2ef059d2025-01-24T13:42:12ZengMDPI AGMicromachines2072-666X2025-01-0116110610.3390/mi16010106Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS InverterBin Wang0Ziyuan Tang1Yuxiang Song2Lu Liu3Weitao Yang4Longsheng Wu5State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaState Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, ChinaIn this paper, a novel p-type junctionless field effect transistor (PJLFET) based on a partially depleted silicon-on-insulator (PD-SOI) is proposed and investigated. The novel PJLFET integrates a buried N+-doped layer under the channel to enable the device to be turned off, leading to a special work mechanism and optimized performance. Simulation results show that the proposed PJLFET demonstrates an I<sub>on</sub>/I<sub>off</sub> ratio of more than seven orders of magnitude, with I<sub>on</sub> reaching up to 2.56 × 10<sup>−4</sup> A/μm, I<sub>off</sub> as low as 3.99 × 10<sup>−12</sup> A/μm, and a threshold voltage reduced to −0.43 V, exhibiting excellent electrical characteristics. Furthermore, a new CMOS inverter comprising a proposed PJLFET and a conventional NMOSFET is designed. With the identical geometric dimensions and gate electrode, the pull-up and pull-down driving capabilities of the proposed CMOS are equivalent, showing the potential for application in high-performance chips in the future.https://www.mdpi.com/2072-666X/16/1/106PD-SOIjunctionless FETburied layerCMOS inverter |
| spellingShingle | Bin Wang Ziyuan Tang Yuxiang Song Lu Liu Weitao Yang Longsheng Wu Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter Micromachines PD-SOI junctionless FET buried layer CMOS inverter |
| title | Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter |
| title_full | Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter |
| title_fullStr | Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter |
| title_full_unstemmed | Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter |
| title_short | Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter |
| title_sort | design and study of a novel p type junctionless fet for high performance of cmos inverter |
| topic | PD-SOI junctionless FET buried layer CMOS inverter |
| url | https://www.mdpi.com/2072-666X/16/1/106 |
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