A high speed processor for elliptic curve cryptography over NIST prime field
Abstract Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a h...
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| Format: | Article |
| Language: | English |
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Wiley
2022-07-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12110 |
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| author | Xianghong Hu Xueming Li Xin Zheng Yuan Liu Xiaoming Xiong |
| author_facet | Xianghong Hu Xueming Li Xin Zheng Yuan Liu Xiaoming Xiong |
| author_sort | Xianghong Hu |
| collection | DOAJ |
| description | Abstract Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a hardware processor which achieves high speed and high security for ECC. We first present a three‐clock cycle, divide‐and‐conquer multiplication algorithm which greatly reduces the number of execution cycles of multiplication. We then propose a dedicated multiplication hardware structure which reuses the multiplier and optimizes data path delay. To keep multiplication running in non‐idle status and executing in parallel with other modular operations, the operation scheduling of point addition and point doubling has been re‐designed and optimized based on an effective segmentation and pipeline strategy. Finally, under the premise of similar computing and hardware overhead, we propose an improved high‐security SM algorithm which involves random points to resist side‐channel attacks. On a 55 nm complementary metal oxide semiconductor application specific integrated circuit platform, the processor costs 463k gates and requires 0.028 ms for one SM. Our results indicate that the ECC processor is superior to other state‐of‐the‐art designs reported in the literature in terms of speed and area‐time product metrics. |
| format | Article |
| id | doaj-art-938225720bcb4cd9b42c911942eac62f |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2022-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-938225720bcb4cd9b42c911942eac62f2025-02-03T06:45:06ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982022-07-0116435035910.1049/cds2.12110A high speed processor for elliptic curve cryptography over NIST prime fieldXianghong Hu0Xueming Li1Xin Zheng2Yuan Liu3Xiaoming Xiong4School of Microelectronics Guangdong University of Technology Guangzhou ChinaSchool of Microelectronics Guangdong University of Technology Guangzhou ChinaSchool of Microelectronics Guangdong University of Technology Guangzhou ChinaSchool of Microelectronics Guangdong University of Technology Guangzhou ChinaSchool of Microelectronics Guangdong University of Technology Guangzhou ChinaAbstract Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a hardware processor which achieves high speed and high security for ECC. We first present a three‐clock cycle, divide‐and‐conquer multiplication algorithm which greatly reduces the number of execution cycles of multiplication. We then propose a dedicated multiplication hardware structure which reuses the multiplier and optimizes data path delay. To keep multiplication running in non‐idle status and executing in parallel with other modular operations, the operation scheduling of point addition and point doubling has been re‐designed and optimized based on an effective segmentation and pipeline strategy. Finally, under the premise of similar computing and hardware overhead, we propose an improved high‐security SM algorithm which involves random points to resist side‐channel attacks. On a 55 nm complementary metal oxide semiconductor application specific integrated circuit platform, the processor costs 463k gates and requires 0.028 ms for one SM. Our results indicate that the ECC processor is superior to other state‐of‐the‐art designs reported in the literature in terms of speed and area‐time product metrics.https://doi.org/10.1049/cds2.12110cryptographydigital integrated circuits |
| spellingShingle | Xianghong Hu Xueming Li Xin Zheng Yuan Liu Xiaoming Xiong A high speed processor for elliptic curve cryptography over NIST prime field IET Circuits, Devices and Systems cryptography digital integrated circuits |
| title | A high speed processor for elliptic curve cryptography over NIST prime field |
| title_full | A high speed processor for elliptic curve cryptography over NIST prime field |
| title_fullStr | A high speed processor for elliptic curve cryptography over NIST prime field |
| title_full_unstemmed | A high speed processor for elliptic curve cryptography over NIST prime field |
| title_short | A high speed processor for elliptic curve cryptography over NIST prime field |
| title_sort | high speed processor for elliptic curve cryptography over nist prime field |
| topic | cryptography digital integrated circuits |
| url | https://doi.org/10.1049/cds2.12110 |
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