Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA
The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths...
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| Format: | Article |
| Language: | English |
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Wiley
2013-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2013/802436 |
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| author | Emna Amouri Habib Mehrez Zied Marrakchi |
| author_facet | Emna Amouri Habib Mehrez Zied Marrakchi |
| author_sort | Emna Amouri |
| collection | DOAJ |
| description | The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-railsignals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number. |
| format | Article |
| id | doaj-art-93212a1d24fb4f29b5d1285cee1fc326 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-93212a1d24fb4f29b5d1285cee1fc3262025-02-03T01:11:55ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092013-01-01201310.1155/2013/802436802436Impact of Dual Placement and Routing on WDDL Netlist Security in FPGAEmna Amouri0Habib Mehrez1Zied Marrakchi2LIP6, Universite Pierre et Marie Curie, 4 Place Jussieu, 75252 Paris, FranceLIP6, Universite Pierre et Marie Curie, 4 Place Jussieu, 75252 Paris, FranceFlexras Technologies, 153 Boulevard Anatole France, 93200 Saint-Denis, FranceThe wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-railsignals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number.http://dx.doi.org/10.1155/2013/802436 |
| spellingShingle | Emna Amouri Habib Mehrez Zied Marrakchi Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA International Journal of Reconfigurable Computing |
| title | Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA |
| title_full | Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA |
| title_fullStr | Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA |
| title_full_unstemmed | Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA |
| title_short | Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA |
| title_sort | impact of dual placement and routing on wddl netlist security in fpga |
| url | http://dx.doi.org/10.1155/2013/802436 |
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