Implementation of a low‐power LVQ architecture on FPGA
This study presents an architecture‐optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy co...
Saved in:
Main Authors: | , , |
---|---|
Format: | Article |
Language: | English |
Published: |
Wiley
2017-11-01
|
Series: | IET Circuits, Devices and Systems |
Subjects: | |
Online Access: | https://doi.org/10.1049/iet-cds.2016.0311 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
_version_ | 1832558541308690432 |
---|---|
author | Najoua Chalbi Mohamed Boubaker Mohamed Hedi Bedoui |
author_facet | Najoua Chalbi Mohamed Boubaker Mohamed Hedi Bedoui |
author_sort | Najoua Chalbi |
collection | DOAJ |
description | This study presents an architecture‐optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy consumption. The low‐power/energy architecture is obtained through the selection of the best one amongst a number of architectures produced by FPGA software design tools that combine power, area and the ergonomic utilisation of internal FPGA resources. A complete characterisation of power at the architectural level was carried out using the Xpower tool. An analytical power model was determined by the following parameters: area, delay and LVQ topology. Concerning the authors’ architecture, there is a 28% gain in the area design. Moreover, it consumes 8% power in the nanoboard 3000 compared with the other ones. |
format | Article |
id | doaj-art-8e4043e00b744161a31ce34ee051c97b |
institution | Kabale University |
issn | 1751-858X 1751-8598 |
language | English |
publishDate | 2017-11-01 |
publisher | Wiley |
record_format | Article |
series | IET Circuits, Devices and Systems |
spelling | doaj-art-8e4043e00b744161a31ce34ee051c97b2025-02-03T01:32:08ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982017-11-0111659760410.1049/iet-cds.2016.0311Implementation of a low‐power LVQ architecture on FPGANajoua Chalbi0Mohamed Boubaker1Mohamed Hedi Bedoui2LTIM Laboratory, Medicine FacultyUniversity of MonastirTunisiaLTIM Laboratory, Medicine FacultyUniversity of MonastirTunisiaLTIM Laboratory, Medicine FacultyUniversity of MonastirTunisiaThis study presents an architecture‐optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy consumption. The low‐power/energy architecture is obtained through the selection of the best one amongst a number of architectures produced by FPGA software design tools that combine power, area and the ergonomic utilisation of internal FPGA resources. A complete characterisation of power at the architectural level was carried out using the Xpower tool. An analytical power model was determined by the following parameters: area, delay and LVQ topology. Concerning the authors’ architecture, there is a 28% gain in the area design. Moreover, it consumes 8% power in the nanoboard 3000 compared with the other ones.https://doi.org/10.1049/iet-cds.2016.0311LVQ topologyanalytical power modelXpower toolergonomic utilisationFPGA software design toolslow-power-energy architecture |
spellingShingle | Najoua Chalbi Mohamed Boubaker Mohamed Hedi Bedoui Implementation of a low‐power LVQ architecture on FPGA IET Circuits, Devices and Systems LVQ topology analytical power model Xpower tool ergonomic utilisation FPGA software design tools low-power-energy architecture |
title | Implementation of a low‐power LVQ architecture on FPGA |
title_full | Implementation of a low‐power LVQ architecture on FPGA |
title_fullStr | Implementation of a low‐power LVQ architecture on FPGA |
title_full_unstemmed | Implementation of a low‐power LVQ architecture on FPGA |
title_short | Implementation of a low‐power LVQ architecture on FPGA |
title_sort | implementation of a low power lvq architecture on fpga |
topic | LVQ topology analytical power model Xpower tool ergonomic utilisation FPGA software design tools low-power-energy architecture |
url | https://doi.org/10.1049/iet-cds.2016.0311 |
work_keys_str_mv | AT najouachalbi implementationofalowpowerlvqarchitectureonfpga AT mohamedboubaker implementationofalowpowerlvqarchitectureonfpga AT mohamedhedibedoui implementationofalowpowerlvqarchitectureonfpga |