Implementation of a low‐power LVQ architecture on FPGA
This study presents an architecture‐optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy co...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2017-11-01
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| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/iet-cds.2016.0311 |
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| Summary: | This study presents an architecture‐optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy consumption. The low‐power/energy architecture is obtained through the selection of the best one amongst a number of architectures produced by FPGA software design tools that combine power, area and the ergonomic utilisation of internal FPGA resources. A complete characterisation of power at the architectural level was carried out using the Xpower tool. An analytical power model was determined by the following parameters: area, delay and LVQ topology. Concerning the authors’ architecture, there is a 28% gain in the area design. Moreover, it consumes 8% power in the nanoboard 3000 compared with the other ones. |
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| ISSN: | 1751-858X 1751-8598 |