Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process
A smart dual‐mode IO driver and termination scheme is proposed and power is efficiently consumed for both low‐speed data transmission under 500 Mbit/s and high‐speed data transmission up to 3.4 Gbit/s. During high speed data transmission, the driver uses near‐ground signalling and pre‐emphasis weigh...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Wiley
2017-03-01
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| Series: | Electronics Letters |
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| Online Access: | https://doi.org/10.1049/el.2016.4290 |
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| _version_ | 1832096681778216960 |
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| author | E. Kim T. Oh |
| author_facet | E. Kim T. Oh |
| author_sort | E. Kim |
| collection | DOAJ |
| description | A smart dual‐mode IO driver and termination scheme is proposed and power is efficiently consumed for both low‐speed data transmission under 500 Mbit/s and high‐speed data transmission up to 3.4 Gbit/s. During high speed data transmission, the driver uses near‐ground signalling and pre‐emphasis weight can be controlled for inter symbol interference (ISI) mitigation. The measured eye shows 17.8% vertically and 19.5% horizontally with finite impulse response (FIR) tap control for 15.75″ FR4 channel. The proto‐type 2 channel single‐ended driver has been implemented in 45 nm CMOS process and occupies 0.022 mm2 chip area. |
| format | Article |
| id | doaj-art-8b4216462ad14425a8e4a84c629bd852 |
| institution | Kabale University |
| issn | 0013-5194 1350-911X |
| language | English |
| publishDate | 2017-03-01 |
| publisher | Wiley |
| record_format | Article |
| series | Electronics Letters |
| spelling | doaj-art-8b4216462ad14425a8e4a84c629bd8522025-02-05T12:30:42ZengWileyElectronics Letters0013-51941350-911X2017-03-0153530831010.1049/el.2016.4290Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS processE. Kim0T. Oh1Department of Electronic EngineeringKwangwoon University615, Bima build., 20, Gwangun‐roNowon‐guSeoul139Republic of KoreaDepartment of Electronic EngineeringKwangwoon University615, Bima build., 20, Gwangun‐roNowon‐guSeoul139Republic of KoreaA smart dual‐mode IO driver and termination scheme is proposed and power is efficiently consumed for both low‐speed data transmission under 500 Mbit/s and high‐speed data transmission up to 3.4 Gbit/s. During high speed data transmission, the driver uses near‐ground signalling and pre‐emphasis weight can be controlled for inter symbol interference (ISI) mitigation. The measured eye shows 17.8% vertically and 19.5% horizontally with finite impulse response (FIR) tap control for 15.75″ FR4 channel. The proto‐type 2 channel single‐ended driver has been implemented in 45 nm CMOS process and occupies 0.022 mm2 chip area.https://doi.org/10.1049/el.2016.4290single‐ended dual‐mode near‐ground transmitter IO driverCMOS processsmart dual‐mode IO drivertermination schemelow‐speed data transmissionhigh‐speed data transmission |
| spellingShingle | E. Kim T. Oh Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process Electronics Letters single‐ended dual‐mode near‐ground transmitter IO driver CMOS process smart dual‐mode IO driver termination scheme low‐speed data transmission high‐speed data transmission |
| title | Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process |
| title_full | Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process |
| title_fullStr | Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process |
| title_full_unstemmed | Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process |
| title_short | Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process |
| title_sort | single ended 2 ch 3 4 gbit s dual mode near ground transmitter io driver in 45 nm cmos process |
| topic | single‐ended dual‐mode near‐ground transmitter IO driver CMOS process smart dual‐mode IO driver termination scheme low‐speed data transmission high‐speed data transmission |
| url | https://doi.org/10.1049/el.2016.4290 |
| work_keys_str_mv | AT ekim singleended2ch34gbitsdualmodeneargroundtransmitteriodriverin45nmcmosprocess AT toh singleended2ch34gbitsdualmodeneargroundtransmitteriodriverin45nmcmosprocess |