Design of 10T SRAM cell with improved read performance and expanded write margin
Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters t...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-01-01
|
| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12006 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|